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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
PM7341, PM8316
S/UNI-IMA-84, TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
PRELIMINARY ISSUE 2: JUNE 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
PUBLIC REVISION HISTORY Issue No. 2 Issue Date June 2001 Details of Change Updated Schematics Added Board Modifications section Modified Software Interface section Inclusion of Bill of Materials Inclusion of Layout Inclusion of VHDL code Updated SEEP register values Minor grammatical and formatting changes 1 December 2000 Document Created.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATIONS ............................................................................ 1 1.3.1 ATM EDGE SWITCH IMA AND UNI PORT CARD ............. 1 1.1.1 ATM MULTISERVICE SWITCH, ANY SERVICE ANY PORT CARD ................................................................................. 2 2 3 FEATURES .............................................................................................. 3 FUNCTIONAL DESCRIPTION................................................................. 4 3.1 DATA FLOW .................................................................................. 4 3.1.1 TRANSMIT DIRECTION..................................................... 4 3.1.2 RECEIVE DIRECTION ....................................................... 7 4 BLOCK DESCRIPTION ......................................................................... 13 4.1 4.2 4.3 4.4 OPTICS ....................................................................................... 13 PM5342 SPECTRA-155.............................................................. 13 PM8316 TEMUX-84 .................................................................... 13 PM7341 S/UNI-IMA-84................................................................ 13 4.4.1 SDRAM............................................................................. 14 4.5 4.6 PM7350 S/UNI-DUPLEX............................................................. 14 BUS INTERFACES ..................................................................... 14 4.6.1 TELECOM BUS INTERFACE........................................... 14 4.6.2 SBI BUS INTERFACE ...................................................... 16 4.6.3 UTOPIA LEVEL 2 BUS INTERFACE ................................ 16
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
4.7 4.8
COMPACTPCI BRIDGE .............................................................. 17 SEEP........................................................................................... 18 4.8.1 CARD ID NUMBER .......................................................... 18 4.8.2 SERIAL EEPROM LOAD REGISTERS ............................ 19
4.9
CPLD........................................................................................... 22 4.9.1 LOCAL BUS GLUE LOGIC............................................... 23
4.10
FULL HOT SWAP CAPABILITY .................................................. 23 4.10.1 POWER SUPPLY WITH HOT SWAP CONTROLLER ..... 24 4.10.2 EJECTOR HANDLE AND LED ......................................... 25
4.11
CPCI BRIDGE HARDWARE INTERFACES................................ 26 4.11.1 CPCI SYSTEM BUS INTERFACE.................................... 26 4.11.2 PCI 9030-LOCAL BUS INTERFACE ................................ 26
4.12 5
OSCILLATORS ........................................................................... 28
ANALYSIS.............................................................................................. 29 5.1 INTERFACE TIMING................................................................... 29 5.1.1 SPECTRA-155 - TEMUX-84 TELECOM DROP BUS ...... 29 5.1.2 SPECTRA-155 - TEMUX-84 TELECOM ADD BUS ......... 30 5.1.3 TEMUX-84 - S/UNI-IMA-84 SBI ADD BUS INTERFACE . 32 5.1.4 TEMUX-84 - S/UNI-IMA-84 SBI DROP BUS INTERFACE33 5.1.5 S/UNI-IMA-84 - S/UNI-DUPLEX UTOPIA LEVEL 2 TRANSMIT BUS INTERFACE.......................................... 36 5.1.6 S/UNI-IMA-84 - S/UNI-DUPLEX UTOPIA LEVEL 2 RECEIVE BUS INTERFACE ............................................ 38 5.1.7 PCI 9030 TIMING DIAGRAMS ......................................... 41 5.2 SIGNAL INTEGRITY SIMULATIONS .......................................... 53
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
5.2.1 PRE-LAYOUT ................................................................... 53 5.2.2 TELECOM BUS................................................................ 53
5.2.3 5.2.4
SBI BUS ........................................................................... 55 UTOPIA L2 BUS ............................................................... 56
5.2.5 PCI 9030 INTERFACE ..................................................... 58 5.3 6 POWER ESTIMATE AND THERMAL ANALYSIS........................ 60
DESIGN ISSUES ................................................................................... 62 6.1 POWER SUPPLY........................................................................ 62 6.1.1 DECOUPLING .................................................................. 62 6.1.2 POWER-UP SEQUENCE................................................. 62 6.2 6.3 6.4 6.5 6.6 SPECTRA-155 DESIGN CONSIDERATIONS ............................ 63 TEMUX-84 DESIGN CONSIDERATIONS ................................... 63 S/UNI-DUPLEX DESIGN CONSIDERATIONS............................ 63 TELECOM, SBI, UTOPIA L2 BUS DESIGN CONSIDERATIONS 63 PCI BRIDGE DESIGN CONSIDERATIONS ................................ 64
7
LAYOUT DESCRIPTION ....................................................................... 65 7.1 7.2 7.3 7.4 COMPONENT PLACEMENT ...................................................... 65 LAYER STACKING AND IMPEDANCE CONTROL..................... 67 PCI BUS SIGNAL SPECIFICATION............................................ 67 ROUTING.................................................................................... 67
8
PHYSICAL AND MECHANICAL DESCRIPTIONS ................................. 68 8.1 8.2 FORM FACTOR .......................................................................... 68 LEDS ........................................................................................... 68 8.2.1 CARD STATUS LEDS ...................................................... 68
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
8.2.2 SPECTRA-155 LED'S ...................................................... 68 9 SOFTWARE INTERFACE...................................................................... 70 9.1 9.2 9.3 9.4 10 SYSTEM PROCESSOR REQUIREMENT .................................. 70 S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT OPERATING SYSTEM...................................................................................... 70 DEVICE DRIVERS ...................................................................... 70 S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT MEMORY MAP 70
BOARD MODIFICATIONS ..................................................................... 72 10.1 10.2 10.3 SIGNAL DETECT ON HFCT 5905 .............................................. 72 UTOPIA L2 BUS.......................................................................... 72 SCANENB PIN ON S/UNI-IMA-84 .............................................. 72
11 12 13 14 15 16
GLOSSARY ........................................................................................... 73 REFERENCES....................................................................................... 74 APPENDIX A: BILL OF MATERIALS ..................................................... 75 APPENDIX B: SCHEMATICS ................................................................ 76 APPENDIX C: LAYOUT ......................................................................... 77 APPENDIX D: VHDL CODE FOR CPLD................................................ 78
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
LIST OF FIGURES FIGURE 1 ATM EDGE SWITCH IMA AND UNI PORT CARD EXAMPLE .......... 2 FIGURE 2 ATM MULTISERVICE SWITCH, ANY SERVICE ANY PORT CARD EXAMPLE...........................................................................................2 FIGURE 3 S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT DATA FLOW ......... 4 FIGURE 4 S/UNI-DUPLEX DEMULTIPLEXING ATM STREAMS....................... 5 FIGURE 5 IMA PROTOCOL ............................................................................... 6 FIGURE 6 SONET OC-3 FRAME PROCESSING BY THE SPECTRA-155 ....... 8 FIGURE 7 VT1.5 DEMAPPING BY THE TEMUX-84........................................ 10 FIGURE 8 BLOCK DIAGRAM OF S/UNI-IMA-84/ TEMUX-84 DEVELOPMENT KIT...................................................................................................12 FIGURE 9 TELECOM BUS INTERFACE ......................................................... 15 FIGURE 10 SBI BUS INTERFACE ................................................................... 16 FIGURE 11 UTOPIA LEVEL 2 BUS INTERFACE ............................................. 17 FIGURE 12 CPLD LOGIC BLOCK DIAGRAM.................................................. 23 FIGURE 14 POWER SUPPLY WITH INTEGRATED HOT SWAP CIRCUITRY 24 FIGURE 15 CPCI SYSTEM BUS INTERFACE BLOCK DIAGRAM.................. 26 FIGURE 16 PCI 9030 LOCAL BUS INTERFACE BLOCK DIAGRAM .............. 27 FIGURE 17 TELECOM DROP BUS TIMING DIAGRAM .................................. 29 FIGURE 18 TELECOM ADD BUS TIMING DIAGRAM ..................................... 31 FIGURE 19 SBI ADD BUS TIMING ANALYSIS ................................................ 32 FIGURE 20 SBI DROP BUS TIMING ANALYSIS ............................................. 34 FIGURE 21 UTOPIA L2 BUS TRANSMIT TIMING DIAGRAM ......................... 37 FIGURE 22 UTOPIA L2 BUS RECEIVE TIMING DIAGRAM............................ 39
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v
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
FIGURE 23 TEMUX-84 READ CYCLE TIMING ............................................... 42 FIGURE 24 TEMUX-84 WRITE CYCLE TIMING ............................................. 43 FIGURE 25 S/UNI-DUPLEX READ TIMING DIAGRAM ................................... 45 FIGURE 26 S/UNI-DUPLEX WRITE TIMING DIAGRAM ................................. 47 FIGURE 27 SPECTRA-155 READ CYCLE TIMING......................................... 49 FIGURE 28 SPECTRA-155 WRITE CYCLE TIMING ....................................... 51 FIGURE 29 TELECOM BUS SIMULATION SCHEMATIC ................................ 53 FIGURE 30 TELECOM DROP BUS SIMULATION RESULTS ......................... 54 FIGURE 31 TELECOM ADD BUS SIMULATION RESULTS ............................ 54 FIGURE 32 SBI BUS SIMULATION SCHEMATIC............................................ 55 FIGURE 33 SBI ADD BUS SIMULATION RESULTS........................................ 55 FIGURE 34 SBI DROP BUS SIMULATION RESULTS..................................... 56 FIGURE 35 UTOPIA L2 BUS SIMULATION SCHEMATIC ............................... 56 FIGURE 36 UTOPIA L2 RECEIVE BUS SIMULATION RESULTS ................... 57 FIGURE 37 UTOPIA L2 TRANSMIT BUS SIMULATION RESULTS................. 57 FIGURE 38 PCI 9030 SIMULATION SCHEMATIC........................................... 58 FIGURE 39 PCI 9030 SIMULATION RESULTS ............................................... 59 FIGURE 40 CARD FLOORPLAN ..................................................................... 66
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
LIST OF TABLES TABLE 1 PCI CARD ID CODES ....................................................................... 18 TABLE 2 PCI 9030 SERIAL EPROM LOAD REGISTERS ............................... 19 TABLE 3 TELECOM DROP BUS PROPAGATION DELAYS ............................ 30 TABLE 4 TELECOM DROP BUS TIMING CONSTRAINTS.............................. 30 TABLE 5 TELECOM ADD BUS PROPAGATION DELAYS ............................... 31 TABLE 6 TELECOM ADD BUS TIMING CONSTRAINTS ................................ 31 TABLE 7 SBI ADD BUS PROPAGATION DELAYS .......................................... 33 TABLE 8 SBI ADD BUS TIMING CONSTRAINTS ............................................ 33 TABLE 9 SBI DROP BUS PROPAGATION DELAYS ....................................... 34 TABLE 10 SBI DROP BUS TIMING CONSTRAINTS ....................................... 36 TABLE 11 UTOPIA L2 TRANSMIT BUS PROPAGATION DELAYS.................. 38 TABLE 12 UTOPIA L2 TRANSMIT BUS TIMING CONSTRAINTS................... 38 TABLE 13 UTOPIA L2 RECEIVE BUS PROPAGATION DELAYS.................... 40 TABLE 14 UTOPIA L2 TRANSMIT BUS TIMING CONSTRAINTS................... 40 TABLE 15 PCI 9030 AC TIMING (LOCAL INPUTS) ELECTRICAL CHARACTERISTICS........................................................................................ 41 TABLE 16 PCI 9030 AC TIMING (LOCAL OUTPUTS) ELECTRICAL CHARACTERISTICS........................................................................................ 41 TABLE 17 PCI 9030 TO TEMUX-84 READ PROPAGATION DELAYS............. 43 TABLE 18 PCI 9030 TO TEMUX-84 READ TIMING CONSTRAINTS .............. 43 TABLE 19 PCI 9030 TO TEMUX-84 WRITE PROPAGATION DELAYS........... 44 TABLE 20 PCI 9030 TO TEMUX-84 WRITE TIMING CONSTRAINTS ............ 44 TABLE 21 PCI 9030 TO S/UNI-DUPLEX READ PROPAGATION DELAYS ..... 46
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
TABLE 22 PCI 9030 TO S/UNI-DUPLEX READ TIMING CONSTRAINTS....... 46 TABLE 23 PCI 9030 TO S/UNI-DUPLEX WRITE PROPAGATION DELAYS ... 48 TABLE 24 PCI 9030 TO S/UNI-DUPLEX WRITE TIMING CONSTRAINTS..... 48 TABLE 25 PCI 9030 TO SPECTRA-155 READ PROPAGATION DELAYS ...... 50 TABLE 26 PCI 9030 TO SPECTRA-155 READ TIMING CONSTRAINTS........ 50 TABLE 27 PCI 9030 TO SPECTRA-622 WRITE PROPAGATION DELAYS... 52 TABLE 28 PCI 9030 TO SPECTRA-622 WRITE TIMING CONSTRAINTS .... 52 TABLE 29 POWER CONSUMPTION BY SUPPLY RAIL FOR EACH DEVICE 60 TABLE 30 S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT MEMORY MAP.. 70
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
1
INTRODUCTION The S/UNI-IMA-84/TEMUX-84 Development Kit is intended for software development of several PMC-Sierra devices including: * * * * SPECTRA-155 TEMUX-84 S/UNI-IMA-84 S/UNI-DUPLEX
1.1
Purpose The S/UNI-IMA-84/TEMUX-84 Development Kit is intended to assist engineers in board design and software development using PMC-Sierra's PM7341 S/UNIIMA-84, PM8316 TEMUX-84, PM5342 SPECTRA-155 and PM7350 S/UNIDUPLEX. The S/UNI-IMA-84/TEMUX-84 Development Kit can also be used to generate a high speed Low Voltage Differential Signal (LVDS) serial link for connection to other PMC-Sierra devices with an LVDS interface.
1.2
Scope This document describes the design of the S/UNI-IMA-84/TEMUX-84 Development Kit. A description for each of the functional blocks of the design is given followed by the detailed design, including physical and mechanical descriptions, implementation descriptions, layout, bill of materials and CPLD code.
1.3 1.3.1
Applications ATM Edge Switch IMA and UNI Port Card An optimized solution comprising the PM7341 S/UNI-IMA-84 and PM8316 TEMUX-84 devices enables a new generation of high-density port cards for terminating up to an OC-3s worth of IMA circuits (84 T1 links). The following Figure shows the S/UNI-IMA-84 connected to a TEMUX-84, SDRAM and an ATM Layer Device.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
PM5342 SPECTRA-155
PM8316 TEMUX-84
PM7341 S/UNI-IMA-84
PM7326 S/UNI-APEX
SDRAM
Telecom Bus
SBI
Utopia L2/ Any-PHY
Figure 1 ATM Edge Switch IMA and UNI Port Card Example 1.1.1 ATM Multiservice Switch, Any Service Any Port Card The following Figure shows an ATM Multiservice Switch Any Service, Any Port card comprising the PM7341 S/UNI-IMA-84, PM7385 FREEDM-84A672, Frame Relay to ATM Interworking Functions, PM73122 AAL1gator-32, PM8316 TEMUX84, PM5342 SPECTRA-155 and a DS3 LIU. Through software configuration of the devices, any port can be configured to support IMA, User-to-Network Interfaces (UNI), Frame Relay or Circuit Emulation Service.
PM7385 FREEDM-84A672
DS3 LIU Frame Relay to ATM Interworking Functions
PM5342 SPECTRA-155
PM8316 TEMUX84
PM7341 S/UNI-IMA-84 PM73122 AAL1gator-32
Telecom Bus
SBI
UTOPIA L2 / Any-PHY
Figure 2 ATM Multiservice Switch, Any Service Any Port Card Example
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2
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
2
FEATURES This Reference Design provides the following features: * * * * * * * Provides full access to the SPECTRA-155, TEMUX-84, S/UNI-IMA-84, S/UNI-DUPLEX registers. 33 MHz CompactPCI (CPCI) interface. On board hot swap controller with power sequencing. 3.3 Volt CMOS Telecom bus allowing communication between the SPECTRA-155 and the TEMUX-84. 19.44 MHz SBI bus allowing communication between the TEMUX-84 and the S/UNI-IMA-84. UTOPIA Level 2 bus allowing communication between the S/UNI-IMA-84 and the S/UNI-DUPLEX. Two LVDS serial links provided for applications that need 1:1 protection such as connection to the DSLAM Core Card (part of the DSLAM Reference Design) for connection to WAN up-link. Front panel status LED's which display line status and power supply status.
*
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
3 3.1
FUNCTIONAL DESCRIPTION Data Flow The S/UNI-IMA-84/TEMUX-84 Development Kit is connected over a CompactPCI bus to a host processor and external memory. Figure 3 illustrates the general data flow.
SONET SPEs SONET OC-3 FRAME
SBI SPEs
ATM Cells LVDS
SPECTRA155
SONET SPEs
TEMUX-84
SBI SPEs text
S/UNI-IMA-84
ATM Cells
S/UNIDUPLEX
Optical Interface
Telecom ADD/DROP Bus
SBI ADD/DROP Bus
UTOPIA L2 Receive/Transmit Bus
LVDS Interface
Figure 3 S/UNI-IMA-84/TEMUX-84 Development Kit Data Flow 3.1.1 Transmit Direction In the transmit direction, the S/UNI-DUPLEX receives data via the LVDS interface. The S/UNI-DUPLEX demultiplexes these ATM cells and routes them to the appropriate virtual PHY of the S/UNI-IMA-84 via the UTOPIA L2 bus.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
Utopia L2 Bus
PHY #1 PHY #2 PHY #3 PHY #4 PHY #1 PHY #2 PHY #3 PHY #4 PHY #1 PHY #2 PHY #3 PHY #4 PHY #1 PHY #2 PHY #3 PHY #4
LVDS Links S/UNI DUPLEX
PHY #1
PHY #2
PHY #3
PHY #4
One Multiplexed ATM Stream Four Single ATM Streams
Figure 4 S/UNI-DUPLEX Demultiplexing ATM Streams The S/UNI-IMA-84 performs the IMA protocol on the data recovered from the UTOPIA L2 bus. The IMA protocol consists of taking a cell stream destined to a group and distributing the cells in a round-robin fashion to the links within a group, adding IMA Control Protocol (ICP) cells, filler cells and stuff cells as needed. The ICP cells convey state information to the far end and are used to format an IMA frame. The IMA frame is used as a mechanism to synchronize the links at the far end. Cell rate decoupling is performed at the IMA sub-layer via filler cells. Filler cells are used instead of physical layer cells for cell rate decoupling, thus a continuous stream of cells is sent to the TC layer. By distributing the ATM cell stream to multiple physical links in a round-robin fashion, an IMA Group appears to the ATM layer devices like a PHY layer device with a maximum capacity which is determined by the number of links per group the S/UNI-IMA-84 is configured to support (e.g. nxT1, nxE1, nxG.SHDSL). The S/UNI-IMA-84 supports up to 42 simultaneous IMA groups and each IMA group can support 1 to 32 links with the constraint of a maximum of 84 total links. However, because the S/UNI-IMA-84 is configured in UTOPIA L2 mode (as opposed to Any-PHY) and because UTOPIA L2 only supports 31 PHYs, only up to a maximum of 31 virtual PHYs can be addressed within the S/UNI-IMA-84. An IMA Group is referred to as a virtual PHY because the ATM layer can address multiple virtual PHYs within one physical PHY device, the S/UNI-IMA-84. In this design, an IMA link refers to the individual T1 line, down which a portion of the Group's ATM traffic travels. An IMA layer device on the other end of the physical links will reassemble the ATM cells arriving from the various physical links into a single ATM stream, which it will pass to the ATM layer.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
Link #1
Single ATM Stream IMA Group
Link #2
Link #3
Figure 5 IMA Protocol In the TC sub-layer, the HEC is calculated and inserted into the cell headers. The cell stream is then mapped into the DS1 payload with zeros inserted for the framing and overhead bits. After a serial to parallel conversion is performed on the 84 links, the data is then conveyed across the SBI ADD bus to the TEMUX-84. The EXSBI (Extract Scaleable Bandwidth Interconnect) block of the TEMUX-84 device demaps up to 84 1.544Mb/s links, 63 2.048Mb/s links or three 44.736Mb/s links from the SBI ADD bus. Timing for the links can be slaved to the arrival rate of data or from link rate adjustments provided by the TEMUX-84. In this design, the TEMUX-84 is configured in master mode. The TEMUX-84 can also send link rate adjustment requests to the S/UNI-IMA-84 using the AJUST_REQ signal. This signal indicates whether the S/UNI-IMA-84 should send one additional or one fewer byte of data during the next 500 s interval. Each T1 transmitter frames to SF or ESF DS1 formats, or framing can be optionally disabled. The TEMUX-84 supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion and zero-code suppression on a per-DS0 basis. PRBS generation or detection is supported on a framed and unframed T1 basis. The SPE's from the TEMUX-84 are transmitted to the SPECTRA-155 devices via the TELECOM ADD Bus.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
Each TPIP (Transmit Pointer Interpreter) block within the SPECTRA-155 takes the SPEs from the TELECOM ADD Bus and interprets the H1, H2 pointers, indicates the J1 byte location, and detects alarm conditions. The TTAL (Transmit Telecombus Aligner) block then takes the STS-1 SPE from the TPIP, and aligns it to the frame of the transmit stream. The TPOP (Transmit Path O/H Processor) block then performs path overhead processing. Following this, both Line and Section Overhead processing occurs before the complete SONET STS-3 SPE is transmitted serially over transmit line interface. The transmitted signal is then converted to optical format by the front panel Optical Interface unit. 3.1.2 Receive Direction The S/UNI-IMA-84/TEMUX-84 Development Kit receives SONET/SDH OC-3 (155.52 Mbits\s) frames through the front panel optical interface. The optical interface converts the optical signals into STS-3 (155.52 Mbits\s) electrical signals for processing by the SPECTRA-155. The SPECTRA-155 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH section (regenerator section), line (multiplexer section), and path. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section and line bit interleaved parity (BIP) (B1, B2), accumulating error counts at each level for performance monitoring purposes. B2 errors are also monitored to detect signal fail and signal degrade threshold crossing alarms (for use with Automatic Protection Switching). Line remote error indications (M1) are also accumulated. In addition, the SPECTRA-155 interprets the received payload pointers (H1, H2), detects path alarm conditions, detects and accumulates path BIPs (B3). The SPECTRA-155 also monitors and accumulates path Remote Error Indications (REIs), accumulates and compares the 16 or 64 byte path trace (J1) message against an expected result, and extracts the Synchronous Payload Envelope (virtual container). Figure 6 below depicts the format of an incoming SONET STS-3 Frame using floating SPE structures. The SPE's are located using the H1 and H2 pointer bytes.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
9 Bytes
SPEn PAYLOAD BYTE #: 1 1 1 2 2 2
261 Bytes
3 3 3 87 87 87
Line Overhead
J1
B H1 H1 H1 H2 H2 H2 H3 H3 H3 C2
9 Bytes Section Overhead
G F2 H
J1 B
S P E #1 S P E #3
S P E #1 S P E #3
S P E #1 S P E #3
Z3 J1 C2 Z4 B G Z5 C2 F2
Line Overhead Frame #2
H1 H1 H1 H2 H2 H2 H3 H3 H3
GH F2 Z3 H Z4 Z5 Z4 Z3 Z5
S P E #2
S P E #2
S P E #2
Section Overhead
SPEn PAYLOAD BYTE #: 1 J1 B
1
1
2
2
2
3
3
3
87 87
87
STS-3 SPE Transported Across Telecom Bus
C2
9 Bytes
G F2 H
J1 B
S P E #1 S P E #3
S P E #1 S P E #3
S P E #1 S P E #3
Z3 J1 C2 Z4 B G Z5 C2 F2 GH F2 Z3 H Z4 Z5 Z4 Z3 Z5 S P E #2
S P E #2
S P E #2
Figure 6 SONET OC-3 Frame Processing by the SPECTRA-155 The extracted SPE is placed on the Telecom DROP bus. The DPL (DROP Bus Payload Active) and DC1J1V1 (DROP Bus Composite Timing) signals indicate the location of the path overhead and the tributaries within the SPE. The TEMUX-84 device receives data placed on the TELECOM DROP Bus. The TEMUX-84 is configured to use a Telecom Bus (SONET\SDH) Line Side Interface and the SBI Bus System Side Interface. The SONET/SDH line side interface provides STS-1 SPE processing and generation. The payload processor aligns and monitors the performance of SONET virtual tributaries (VT1.5s). Maintenance functions per tributary include loss of pointer detection, AIS alarm, tributary path signal label mismatch, and tributary path signal label unstable alarms. Optionally, interrupts can be generated due to the assertion and removal of any of the above alarms. Counts
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
are accumulated for tributary path BIP-2 errors on a block or bit basis and for FEBE indications. The synchronous payload envelope generator generates all tributary pointers and calculates and inserts tributary path BIP-2. The generator also inserts FEBE, RDI and enhanced RDI in the V5 byte. Software can force AIS insertion on a per tributary basis. The TEMUX-84 SONET/SDH VT Payload Processor demaps up to 84 T1s from the three STS-1 SPEs (AU3 or TUG3). The bit asynchronous demapper performs majority vote C-bit decoding to detect stuff requests for T1, E1 and DS3 asynchronous mappings. The VT1.5/VT2/TU-11/TU-12 mapper uses an elastic store and a jitter attenuator to minimize jitter introduced via bit stuffing. Figure 7 depicts how the individual STS-1 SPE's (carried within the STS-3 SPE) transmitted across the Telecom Drop Bus are processed by the TEMUX-84. The TEMUX-84 is configured to process three STS-1 SPEs and it utilizes the tributary pointers to locate the beginning of each VT1.5. Figure 7 also shows how each VT1.5 is mapped into the STS-1 SPE.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
SPEn PAYLOAD BYTE #: 1 J1 B
1
1
2
2
2
3
3
3
87 87
87
STS-3 SPE Transported Across Telecom Bus
9 Bytes
C2 G F2 H
S P J1 E B #1 Z3 J1 C2 Z4 B G Z5 C2 F2 GH F2 Z3 H Z4 Z3 Z5 Z4 Z5 S P E #2
S P E #1 S P E #3 S P E #3
S P E #1 S P E #3
S P E #2
S P E #3
Path Overhead
J1 B C2 G F2 H Z3 Z4 Z5 2 3 87
3 STS-1 SPE Processed by TEMUX-84
Path Overhead
Fixed Stuff
J1 B Tributary Pointers R R VT VT VT 1.5 R 1.5 1.5 #28 R #1 #2 R R R R R R R R VT R VT VT 1.5 R 1.5 1.5 #28 R #1 #2 R R R VT 1.5 #28
Mapping of 28 VT1.5's into an STS-1 SPE
C2 G VT VT 9 Bytes F2 1.5 1.5 H #1 #2 Z3 Z4 Z5
DS0# 1, 4, 7,...,22 DS0# 2, 5, 8,...,23 DS0# 3, 6, 9,...,24
Figure 7 VT1.5 Demapping by the TEMUX-84 The S/UNI-IMA-84 implements the Transmission Convergence (TC) layer function and Inverse Multiplexing for ATM (IMA) protocol for DS1/E1 links. The TC layer searches for cell delineation as per the procedures outlined in ITUT Recommendation I.432.1. To find the cell delineations, the TC layer computes the HEC value for all bits received. Once cell delineation is obtained, the payload is optionally descrambled and the cells are passed to the IMA sub-layer. The TC layer provides counts of errored headers as well as OCD and LCD error interrupts.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
The IMA sub-layer performs IMA frame delineation and stuff cell removal. IMA delineation consists of reassembling a single ATM stream, running at some multiple of the T1 rate, out of the ATM cells arriving over the multiple physical links. Based upon the ICP cell information, the S/UNI-IMA-84 determines the differential delay between the links within a group and applies the link and group state machine logic to coordinate the activation and deactivation of the groups and links with the far end. The recovered ATM cells are transmitted across a Utopia L2 interface running at 25 MHz to the S/UNI-DUPLEX. The S/UNI-DUPLEX implements the first stage of multiplexing by routing traffic from the IMA's virtual PHYs and transmitting the traffic simultaneously over two high speed serial 4 wire LVDS providing 1:1 protection for possible interface to a core card for connection to a WAN up-link.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
Status Outputs
OC-3 Line
HFCT 5905
STS-3
TX RX I/F Control I/F
Spectra-155 PM5342
Telecom Add Telecom Drop
L E D S
19.44 MHz Telecom Bus Add Bus Drop Bus
Telecom Add Control I/F SBI Add Telecom Drop SBI Drop
Temux-84 PM8516
19.44 MHz SBI Bus Add Bus Drop Bus
SBI Drop SBI Add Control I/F Transmit
SDRAM
S/UNI IMA-84 PM7341
Receive
Transmit Receive Utopia Level 2
Transmit Receive
S/UNI DUPLEX PM7350
Control I/F
LVDS TX/RX
CPLD
I/O
LVDS Bus
L V D S
Oscillators
PCI Controller PLXPCI9030
5V / 3.3V /1.8V Regulators, Hot-Swap Controller Primary PCI Bus
C P C I
Figure 8 Block Diagram of S/UNI-IMA-84/ TEMUX-84 Development Kit
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
4
BLOCK DESCRIPTION The following sections describe the function of each hardware block shown in Figure 8.
4.1
Optics Conversion between the optical OC-3 signal and the electrical STS-3 signal is accomplished using the HP HFCT-5905 optical transceiver.
4.2
PM5342 SPECTRA-155 The PM5342 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER (SPECTRA-155) terminates the transport and path overhead of STS-1 (STM-0/AU3) and STS-3/3c (STM-1/AU3/AU4) streams at 51.84 Mbit/s and 155.52 Mbit/s respectively. The SPECTRA-155 implements significant functions for a SONET/SDH compliant line interface. The SPECTRA-155 is implemented in low power, +5 Volt, CMOS technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and is packaged in a 256-pin SBGA package.
4.3
PM8316 TEMUX-84 The TEMUX-84 is a high density T1/E1 framer with integrated VT/TU Mappers and M13 Multiplexers. PM8316 provides framing and multiplexing for 84 T1 channels or 63 E1 channels into three channelized DS-3's or alternatively maps the T1/E1 channels directly into a SONET/SDH OC-3. The TEMUX-84 is configured for a Telecom Bus Line Side Interface, and a Scaleable Bandwidth Interconnect (SBI) Bus System Side Interface. The Telecom bus is used to transfer SONET Synchronous Payload Envelopes (SPE) between the SPECTRA-155 and the TEMUX-84. The SBI bus is used to interface to a link layer device, in this case the S/UNI-IMA-84.
4.4
PM7341 S/UNI-IMA-84 The PM7341 S/UNI-IMA-84 is a monolithic integrated circuit that implements the Inverse Multiplexing for ATM protocol over up to 84 T1 links or 63 E1 links when using the high density SBI interface or 32 independent T1/E1 links using the clock and data interface. The S/UNI-IMA-84 can support up to 42 simultaneous IMA groups and each IMA group can support 1 to 32 links with a maximum of 84 links in total. Each group can consist of either T1 or E1 links. Alternatively, the
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
S/UNI-IMA-84 can be used for cell delineation of up to 84 T1 links, 63 E1 links or 3 DS3 links. 4.4.1 SDRAM Two configurations of external SDRAM are supported, 16Mbit (1Mbit x 16) and 64 Mbit (4Mbit x 16), both of which are single chip devices. 4.5 PM7350 S/UNI-DUPLEX The PM7350 S/UNI-DUPLEX is a monolithic integrated circuit, typically used with its sister device, the S/UNI-VORTEX, to implement a point-to-point serial backplane interconnect architecture. The primary role of the S/UNI-DUPLEX is to interface to up to 32 devices (typically framers or PHYs) and transfer 52-56 byte data cells in serial format to/from a backplane. Devices interface to the S/UNI-DUPLEX via an 8 or 16-bit SCI-PHY/UTOPIA/Any-PHY bus, or optionally via a 16-port clock and data interface. Each S/UNI-DUPLEX can connect to two 100 to 200 Mb/s Low Voltage Differential Signal (LVDS) serial links. A microprocessor port provides access to internal configuration and monitoring registers. The microprocessor port may also be used to insert and extract cells in support of an embedded microprocessor communication channel. 4.6 Bus Interfaces
4.6.1 Telecom Bus Interface The Telecom bus is used to transfer SONET Synchronous Payload Envelopes (SPE) between the SPECTRA-155 and the TEMUX-84 devices. The connectivity is as shown in Figure 9.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
Ref. Clock Source
REFCLK 19.44 MHz
Telecom DROP BUS
Telecom ADD BUS
LAC1 and DFP from CPLD
Vss
TEMUX-84 Telecom Bus Section
L77 LREFCLK
SPECTRA-155 Telecom Bus Section
DCK DFP DD[7:0] DPL DC1J1V1 DDP ACK AD[7:0] APL AC1J1V1/AFP ADP
LAC1 LAC1J1V1 LADATA[7:0] LADP LAPL LDC1J1V1 LDDATA[7:0] LDDP LDPL
Figure 9 Telecom Bus Interface In the receive direction, the SONET Payload is presented to the Telecom DROP bus to be received by the TEMUX-84. The TEMUX-84 will terminate the SONET Payload, demultiplex and remap the VT1.5 data into T1 data that will be sent to the S/UNI-IMA-84. In the transmit direction, the TEMUX-84 drives the Telecom ADD bus. The transmitted SPE is then received and processed by the SPECTRA-155 device. The TEMUX-84 utilizes the LAC1 signal to identify the frame and multiframe boundaries on the Add data bus. The signal is generated in the CPLD by dividing a 19.44 MHz clock by 9720. The SPECTRA-155 (DFP) also uses this frame pulse.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
4.6.2 SBI Bus Interface The TEMUX-84 device features a Scaleable Bandwidth Interconnect (SBI) bus to interface to link layer devices like the S/UNI-IMA-84. The SBI bus connectivity between TEMUX-84 and the S/UNI-IMA-84 is shown in Figure 10.
DROP BUS
ADD BUS
19.44 MHz Clock Driver
TEMUX-84
SREFCLK SC1FP SDDATA(7:0) SDPL SDDP SDV5 SADATA(7:0) SAPL SADP SAV5 SAJUST_REQ SAC1FP SDC1FP REFCLK
IMA-84 PM7341
DDATA(7:0) DPL DDP DV5 ADATA(7:0) APL ADP AV5 AJUST_REQ AC1FP DC1FP
Figure 10 SBI Bus Interface In the receive direction, the TEMUX-84 will transmit a SPE composed of T1/E1's or DS3's to the S/UNI-IMA-84 via the SBI DROP bus. In the transmit direction, the S/UNI-IMA-84 will transmit SPE's to the TEMUX-84 device via the SBI ADD Bus. The SBI bus utilizes the C1FP signal to indicate SBI Bus multiframe alignment, which occurs every 500 s. The signal is provided by the TEMUX-84. 4.6.3 UTOPIA Level 2 Bus Interface The UTOPIA Level 2 bus is used to transfer ATM cells between the S/UNI-IMA84 and the S/UNI-DUPLEX. The S/UNI-DUPLEX serves as the bus master and continuously polls the S/UNI-IMA-84 for transmit (receive) data. Note that for this kit, the UTOPIA Level 2 bus shall run on an external 25 MHz oscillator; however the S/UNI-DUPLEX and the S/UNI-IMA-84 can support a maximum UL2 bus rate of 52 MHz. The UTOPIA L2 interface is software selectable to be 8 or 16 bits wide. This kit is designed for a 16-bit wide UTOPIA L2 bus. The architecture is as shown in Figure 11.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
25 MHz Bus Clock
TRANSMIT BUS
RECEIVE BUS
PM7341 S/UNI-IMA-84
TCLK TPA TENB TSOC
OFCLK OCA OENB OSOC OADR[0:4] ODAT[0:15] OPRTY IFCLK
PM7350 DUPLEX
TADR[0:4] TDAT[0:15] TPRTY
RCLK RCA RENB RSOC RADR[0:4] RDAT[0:7] RPRTY
ICA IENB ISOC IADR[0:4] IDAT[0:7] IPRTY
Figure 11 UTOPIA Level 2 Bus Interface 4.7 CompactPCI Bridge The S/UNI-IMA-84/TEMUX-84 Development Kit does not have an onboard microprocessor and so the PCI bus host processor card interfaces with this development kit via a CPCI bridge device, which only utilizes a read/write (nonburst) register sequence and interrupt service. The hot swap compatible PLX PCI 9030 (PCI 9030) Bus Target is employed as the CPCI bus interface. The PCI 9030 has a 32 long word (lword) write FIFO and 16 lword read FIFO allowing the CPCI bus to burst data to and from the external microprocessor and the PMC-Sierra devices. The Local bus interface of the PCI 9030 is generic and very flexible, supporting 8, 16, and 32-bit transfers operating in multiplexed or non-multiplexed modes as big or little endian at a clock rate asynchronous to the PCI bus up to 60MHz. The Local bus is partitioned into 4 distinct user-definable address spaces that can be configured independently. Each Local address
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
space can be configured to optionally support burst mode transfers and prefetching. The timing of each address space is specifiable via a set of programmable wait states as well as supporting a ready signal used to insert additional wait states. In this development kit, the host processor will access the Local devices via the PCI 9030 CPCI Bridge configured in non-multiplexed 16-bit address and 16-bit data bus mode. The Local bus is clocked at 33MHz by looping the buffered PCI clock output (BCLKO) available from the PCI 9030 back to the Local bus clock input. The PCI 9030 is designed to operate with either a 33 or 66 MHz PCI bus in a +3.3 V signaling environment, but is also +5 V tolerant on its PCI interface. 4.8 SEEP The NM93CS56 Serial EEPROM from Fairchild Semiconductor is used to store configuration information for the PCI 9030 Bridge. This specific SEEP (or equivalent) is required by PCI 9030 because it supports sequential read operations. The SEEP is 1Kbit deep, 256 bits of which are occupied by the PCI 9030 configuration data, leaving 768 bits unused. The SEEP clock is 250 kHz, which is derived from the PCI clock of 33 MHz internally divided by 132. 4.8.1 Card ID Number The Applications specific Card number is stored in the serial EEPROM. The Card ID assignment is shown in Table 1 below. Table 1 PCI Card ID Codes
Device Unconfigured PCI 9030 Vendor ID 10B5h Device ID 9030h Subsystem Vendor ID 11F8h (PMCSierra) Subsystem ID 2356h S/UNI-IMA84/TEMUX-84 Development kit Issue 1
The 11F8 hex is PMC-Sierra's registered vendor ID. Subsystem ID 2356 hex is unregistered ID for the S/UNI-IMA-84/TEMUX-84 Development kit Issue 1.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
4.8.2 Serial EEPROM Load Registers The PCI 9030 can be initialized to a large extent by reading data from its serial EEPROM port during initialization. Reading the data from the serial EEPROM is equivalent to directly writing to the 9030's configuration registers via the CPU. The S/UNI-IMA-84/TEMUX-84 Development kit includes an EEPROM for this purpose. Table 2 illustrates the preliminary serial EEPROM Load Registers' contents. Refer to the PCI 9030 datasheet for detailed information on the format of the configuration data stored in the SEEP. Table 2 PCI 9030 Serial EPROM Load Registers
SEEP Offset 0h 2h 4h 6h Ah 8h Ch Eh 10h 12h 14h 16h 18h 1Ah Device ID Vendor ID PCI Status PCI Command Class Code Class Code / Revision Subsystem ID Subsystem Vendor ID MSW New Capability Pointer LSW New Capability Pointer (Maximum Latency and Minimum Grant are not loadable) Interrupt Pin (Interrupt Line Routing is not loadable) MSW of Power Management Capabilities LSW of Power Management Next Capability Pointer / Power Management Capability ID 1Ch MSW of Power Management Data / PMCSR Bridge Support Extension 1Eh 20h 22h LSW of Power Management Control / Status MSW of Hot Swap Control / Status LSW of Hot Swap Next Capability Pointer / Hot Swap Control 24h PCI Vital Product Data Address Reserved 0000h PMCSR[14:8] Reserved HS_NEXT[7:0] / HS_CNTL[7:0] 0000h XXXXh 4C06h Reserved XXXXh Description PCI 9030 Register Bits Affected PCIIDR[31:16] PCIIDR[15:0] PCISR[15:0] PCIICR[ PCICCR[23:8] PCICCR[7:0] / PCIREV[7:0] PCISID[15:0] PCISVID[15:0] Reserved CAP_PTR[7:0] Reserved PCIIPR[7:0] / PCIILR[7:0] PMC[14:11, 5, 3:0] PMNEXT[7:0] / PMCAPID[7:0] 9030h 10B5h 0290h 0000h 0001h 0680h 2356h 11F8h XXXXh XX40h XXXXh 0100h 4801h 4801h Setting
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
SEEP Offset 26h
Description
PCI 9030 Register Bits Affected
Setting
PCI Vital Product Next Capability Pointer / PCI Vital Product Data Control
PVPD_NEXT[7:0] / PVPDCNTL[7:0] LAS0RR[31:16] LAS0RR[15:0] LAS1RR[31:16] LAS1RR[15:0] LAS2RR[31:16] LAS2RR[15:0] LAS3RR[31:16] LAS3RR[15:0] EROMRR[31:16] EROMRR[15:0] LAS0BA[31:16]
0003h
28h 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ah 3Ch
MSW of Range for PCI-to-Local Address Space 0 LSW of Range for PCI-to-Local Address Space 0 MSW of Range for PCI-to-Local Address Space 1 LSW of Range for PCI-to-Local Address Space 1 MSW of Range for PCI-to-Local Address Space 2 LSW of Range for PCI-to-Local Address Space 2 MSW of Range for PCI-to-Local Address Space 3 LSW of Range for PCI-to-Local Address Space 3 MSW of Range for PCI-to-Local Expansion ROM LSW of Range for PCI-to-Local Expansion ROM MSW of Local Base Address (Remap) for PCI-to-Local Address Space 0
0FF0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h FFFFh 0000h 0000h
3Eh
LSW of Local Base Address (Remap) for PCI-to-Local Address Space 0
LAS0BA[15:0]
0001h
40h
MSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
LAS1BA[31:16]
0000h
42h
LSW of Local Base Address (Remap) for PCI-to-Local Address Space 1
LAS1BA[15:0]
0000h
44h
MSW of Local Base Address (Remap) for PCI-to-Local Address Space 2
LAS2BA[31:16]
0000h
46h
LSW of Local Base Address (Remap) for PCI-to-Local Address Space 2
LAS2BA[15:0]
0000h
48h
MSW of Local Base Address (Remap) for PCI-to-Local Address Space 3
LAS3BA[31:16]
0000h
4Ah
LSW of Local Base Address (Remap) for PCI-to-Local Address Space 3
LAS3BA[15:0]
0000h
4Ch
MSW of Local Base Address (Remap) for Expansion ROM
EROMBA[31:16]
0010h
4Eh
LSW of Local Base Address (Remap) for Expansion ROM
EROMBA[15:0]
0000h
50h
MSW of Bus Region Descriptors for Local Address Space 0
LAS0BRD1[31:16]
5481h
52h
LSW of Bus Region Descriptors for Local Address Space 0
LAS0BRD1[15:0]
0080h
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
SEEP Offset 54h
Description
PCI 9030 Register Bits Affected
Setting
MSW of Bus Region Descriptors for Local Address Space 1
LAS1BRD1[31:16]
0000h
56h
LSW of Bus Region Descriptors for Local Address Space 1
LAS1BRD1[15:0]
0000h
58h
MSW of Bus Region Descriptors for Local Address Space 2
LAS2BRD1[31:16]
0000h
5Ah
LSW of Bus Region Descriptors for Local Address Space 2
LAS2BRD1[15:0]
0000h
5Ch
MSW of Bus Region Descriptors for Local Address Space 3
LAS3BRD1[31:16]
0000h
5Eh
LSW of Bus Region Descriptors for Local Address Space 3
LAS3BRD1[15:0]
0000h
60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h
MSW of Bus Region Descriptors for Expansion ROM LSW of Bus Region Descriptors for Expansion ROM MSW of Chip Select (CS) 0 Base and Range LSW of Chip Select (CS) 0 Base and Range MSW of Chip Select (CS) 1 Base and Range LSW of Chip Select (CS) 1 Base and Range MSW of Chip Select (CS) 2 Base and Range LSW of Chip Select (CS) 2 Base and Range MSW of Chip Select (CS) 3 Base and Range LSW of Chip Select (CS) 3 Base and Range Serial EEPROM Write-Protected Address Boundary LSW of Interrupt Control / Status Register MSW of PCI Target Response, Serial EEPROM, and Initialization Control
EROMBRD[31:16] EROMBRD[15:0] CS0BASE[31:16] CS0BASE[15:0] CS1BASE[31:16] CS1BASE[15:0] CS2BASE[31:16] CS2BASE[15:0] CS3BASE[31:16] CS3BASE[15:0] PROT_AREA[7:0] INTCSR[15:0] CNTRL[31:16]
0000h 0000h 0002h 0001h 0006h 0001h 000Ah 0001h 000Eh 0001h 0030h 0000h 0078h
7Ah
LSW of PCI Target Response, Serial EEPROM, and Initialization Control
CNTRL[15:0]
0000h
7Ch 7Eh 80h
MSW of General Purpose I/O Control LSW of General Purpose I/O Control MSW of Hidden Power Management Data Select (refer to Section 7.2.1 of PCI 9030 Data sheet)
GPIOC[31:16] GPIOC[15:0] PMDATA[7:0] hidden, D0 and D3hot Power Dissipated PMDATA[7:0] hidden, D0 and D3hot Power Consumed
0000h 0240h 0000h
82h
LSW of Hidden Power Management Data Select (refer to Section 7.2.1 of PCI 9030 Data sheet)
0000h
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
SEEP Offset 84h
Description
PCI 9030 Register Bits Affected
Setting
MSW of Hidden Power Management Data Scale (refer to Section 7.2.1 of PCI 9030 Data Sheet)
Reserved
0000h
86h
LSW of Hidden Power Management Data Scale (refer to Section 7.2.1 of PCI 9030 Data Sheet)
PMCSR[14:13] hidden, Bits[7:0] are used as follows: [7:6] D3hot Power Dissipated [5:4] D0 Power Dissipated [3:2] D3hot Power Consumed [1:0] D0 Power Consumed
0000h
87100h
Blank
4.9
CPLD A Xilinx XC9536XL CPLD provides the miscellaneous logic required for the board, and framing pulses that is required by the SPECTRA-155 as shown in Figure 12. The timing requirements for the design were such to allow the slowest speed grade of XC9536XL available (-10) to be used. Faster pincompatible devices are available should future requirements have tighter timing constraints. Pin compatible devices with more internal logic resources are also available. The logic for the CPLD is specified exclusively in a single VHDL source file. The VHDL code is available in APPENDIX D: VHDL Code for CPLD. 16 of the 34 I/O pins available are used. 14 of the remaining I/O pins are accessible via headers. The CPLD is programmed via its JTAG port. The JTAG port is accessible through the debug header. This interface allows for the possibility of remote upgrades of the CPLD configuration.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
RX8K from DUPLEX
unused
TX8K to DUPLEX
LREFCLK to TEMUX-84 SREFCLK to TEMUX-84 REFCLK to S/UNI-IMA-84 TRCLK\RRCLK to SPECTRA-155 ACK\DCK to SPECTRA-155
19.44 MHz oscillator
Frame Pulse generation
DFP to SPECTRA-155 LAC1 to TEMUX-84 CTCLK to TEMUX-84
Divide by 2430
Figure 12 CPLD Logic Block Diagram 4.9.1 Local Bus Glue Logic Some additional logic is required to glue the interrupt bits from the four PMCSierra devices to the PCI bridge Local bus. The four interrupts from devices are decoded to two interrupt bits to the PCI bridge. All four interrupt bits are also sent to General Purpose I/O pins of the PCI bridge. 4.10 Full Hot Swap Capability Hot swap functionality allows the orderly insertion and removal of boards without adversely affecting system operation. The S/UNI-IMA-84/TEMUX-84 development kit is a Full Hot Swap board. Full Hot Swap boards have the minimum Hot Swap features plus the additional resources for software connection control. The following Full Hot Swap resources are provided to software executing on the external microprocessor: * An ENUM# signal, which is an open collector (open drain) bussed signal, to signal a change in status for the board.
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PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
* * *
A switch, actuated with the lower ejector handle, indicates the beginning of the extraction process or end of the insertion process. An LED to indicate the status of the software connection process. A set of four control and status bits on each board which allows the system host's software to determine the source of the ENUM# signal and control the LED.
This development kit employs a hot swap compatible CPCI bridge, PCI 9030, and a hot swap controller, the Linear Technology LTC1422. The CPCI connector is assembled with three different length pins, as required by the hot swap specification [PICMG 2.1 R1.0]. Supporting circuitry is also carefully designed to not impair the hot swap ability. Please refer to the PCI 9030 data sheet and the CompactPCI Hot Swap Specification, R1.0 for further details regarding these resources. 4.10.1 Power Supply with Hot Swap Controller The power supply for the S/UNI-IMA-84/TEMUX-84 Development Kit is as shown in Figure 13. Integral to the circuit is the use of the LTC1422 Hot Swap Controller.
+ 1.8 V
CompactPCI Connector
+3.3V +5V
0.005 Q1
+ 5V
LT3966
+ 3.3V Q3
LT1585
10 1M 0.047uF 0.022uF
6K81
10 10K
5V_LONG
4K7 4K7 4K7 Q2
LTC1422
SENSE VCC ON TIMER 0.33uF FB GATE RESET 2K43
GND Shortest EARLY GND
To Reset Circuit
Figure 13 Power Supply with integrated hot swap circuitry The S/UNI-IMA-84/TEMUX-84 Development Kit contains components that operate at 1.8V, 3.3V and 5V, referenced to ground. The 5V supply is provided
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S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
to the board through the CompactPCI connector. The 1.8V and 3.3V supplies are generated on the board via DC-DC voltage regulators. It is required that 5V power is provided before both 1.8V and 3.3V power to avoid device latchup. Please refer to the respective data sheets of each device for further details regarding device power-up. The first mating pins are 5V_LONG and Early GND. When these pins initially mate, Q2 saturates and the ON pin of the LTC1422 is held low. The LT1422 has yet to receive power, which keeps both MOSFETs open (off). When the shortest pins mate with the backplane, GND_Shortest connecting to the base of Q2 causes Q2 to turn off and the ON pin then becomes logic high. The LTC1422 then begins to slowly ramp up the gate voltage for Q1 & Q3, causing the MOSFETS to gradually turn on, limiting the inrush current to the board to a safe level. This, in turn, causes the gate voltages on Q1 and Q3 to rise, turning the transistors on. Because the resistor and capacitor network used for Q3 is different than Q1, Q3 powers up with a 20 ms delay. Once Q1 and Q3 turn on, the LP3966 is used to generate the +1.8V supply from the CompactPCI +3.3V line, while the LT1585 generates +3.3V from the CompactPCI +5V line. The board +5V supply is generated directly from the CompactPCI +5V line. The LP3966 is capable of supplying 3A, while the LT1585 can supply 4.6A. Should the voltage across the 0.005 resistor exceed 50 mV for more than 10 s, an internal circuit breaker will trip, pulling the GATE output voltage to ground. 4.10.2 Ejector Handle and LED The ejector handle has a built-in microswitch, which toggles when the ejector changes position. A blue LED signals the card's readiness for removal. When the ejector handle switch is opened the PCI9030 asserts ENUM# to inform the host CPU that the card is about to be removed. When the blue LED is turned on, the card may be safely removed.
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4.11 CPCI Bridge Hardware Interfaces 4.11.1 CPCI System Bus Interface The host processor located on an external board will access the PMC-Sierra devices located on-board through a CPCI connector. The serial EEPROM (SEEP) is used to store configuration information for the PCI 9030 bridge. The system bus interface is a straightforward pin-to-pin connection between both the CPCI connector to the PCI 9030 and the SEEP to the PCI 9030. The system bus pins consist of interface control, address/data control and error reporting. For further functional description of each pin, please refer to any standard book covering PCI technology as well as the PCI 9030 and SEEP datasheet.
cPCI CONNECTOR
DEVSEL IDSEL DEVICE SELECT ID SELECT TARGET READY INITIATOR READY INITIATOR STOP CYCLE FRAME PARITY DEVSEL IDSEL TRDY IRDY STOP FRAME PAR
INTERFACE CONTROL
TRDY IRDY STOP FRAME PAR
SYSTEM
CLK RST
PCI CLOCK RESET
PCLK RST
PLX PCI 9030
ADDRESS/DATA AND COMMAND
C/BE[0:3] AD[0:31]
BYTE ENABLE BUS PCI ADDRESS/DATA BUS
C/BE[0:3] AD[0:31]
ERROR REPORTING
PERR SERR
DATA PARITY ERROR SYSTEM ERROR
PERR SERR EEDO EECS EESK SERIAL EEPROM DATA OUT SK SERIAL DATA CLOCK EEDI SERIAL EEPROM DATA IN
SERIAL EEPROM CHIP SELECT
SEEP NM93CS46
Figure 14 CPCI System Bus Interface Block Diagram 4.11.2 PCI 9030-Local Bus Interface The PCI 9030 serves as a master device on the Local bus. Upon control from the external processor on the System side bus, the PCI 9030 sends the address and data out to the Local bus, while its control information is sent to the CPLD, which handles all decode logic and timing requirements for each PMC-Sierra device. The PCI 9030 is configured to operate the Local Bus in non-multiplexed mode. Access to each PMC-Sierra device by the PCI 9030 is very similar in operation, with the difference between each access being the number of address and data
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DO
CS
DI
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interface pins that each PMC-Sierra device microprocessor block contains, and the set-up and hold timing parameters.
CSB RDB WRB INTB RSTB
ADDR[0:9] DATA[0:7]
SPECTRA-155 PM5342
ALE
ADDR[0:15]
DATA[0:15]
CSB RDB WRB INTB RSTB
ADDR[0:12] DATA[0:7]
CS0 CS1 CS2 CS3
TEMUX-84 PM8316
ALE
PLX PCI 9030
RD# WR# INTB[0:3] RSTB CSB RDB WRB INTB RSTB ADDR[1:10] DATA[0:15]
VCC
BCLK
LCLK
S/UNI IMA-84 PM7341
ALE
CSB RDB WRB INTB RSTB
ADDR[0:7] DATA[0:7]
S/UNI DUPLEX PM7350
ALE
Figure 15 PCI 9030 Local Bus Interface Block Diagram
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4.12 Oscillators A 19.44 MHz 20ppm oscillator is required on the card to drive the Telecom bus and SBI bus. The CPLD will use this clock source to generate the 2 kHz synchronization pulse and other framing pulses. A 37.056 MHz 32ppm oscillator is required on the card to drive the digital phase locked loop on the TEMUX-84 that performs jitter attenuation on the T1 recovered clocks. A 49.152 MHz 32ppm oscillator is required on the card to drive the digital phase locked loop on the TEMUX-84 that performs jitter attenuation on the E1 recovered clocks. A 51.84 oscillator is required on the card to generate a gapped DS3 clock for the TEMUX-84. A 55 MHz oscillator is required on the card to drive the system clock of the S/UNI-IMA-84 for use with the external SDRAM device. A 25 MHz oscillator is required on the card to drive the UTOPIA Level 2 bus.
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5 5.1
ANALYSIS INTERFACE TIMING In the timing analysis figures of the section, a gray waveform indicates uncertainty, and a black waveform indicates an input that is not valid since more than one device may be driving the signal at that time. All times are measured in nanoseconds (ns).
5.1.1 SPECTRA-155 - TEMUX-84 Telecom DROP Bus The Telecom DROP Bus is the ingress interface between SPECTRA-155 data and control outputs and TEMUX-84 data and control inputs. On the DROP bus, DCK provides timing to the SPECTRA-155 and LREFCLK provides timing to the TEMUX-84. These clocks need to be synchronized for correct operation of the bus. The Telecom bus is synchronized to a 19.44 MHz clock source. The AC1J1V1 signal is sampled on the rising edge of LREFCLK and indicates frame, payload and tributary multiframe boundaries. See Figure 16 below for a diagram of the Telecom drop bus timing.
0ns 50ns 100ns 150ns
DCK, LREFCLK tSDFP SPECTRA Input: DFP tPDX Telecom Drop Bus tSTEL tHTEL tPDX tSTEL tHTEL tPDX tSTE L tHTEL tPDX tHDFP
Figure 16 Telecom DROP Bus Timing Diagram In reference to Figure 16, the sequence of events for one Telecom DROP bus clock cycle is as follows: 1. The SPECTRA-155 updates DD[7:0], DDP, DPL, and DC1J1V1 on the rising edge of DCK after a propagation delay, tP Dx. 2. On the next rising edge, the TEMUX-84 samples LDDATA[7:0], LDDP, LDPL, and LDC1J1V1 on the rising edge of LREFCLK. The TEMUX-84 inputs require a set-up time of tS TEL and a hold time of tH TEL relative to the rising edge of LREFCLK.
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3. On the same rising edge of DCK, the SPECTRA-155 samples DFP. DFP requires a set-up time of tS DFP and a hold time of tH DFP. The output propagation delays involved in Figure 16 are shown in the following table: Table 3 Telecom Drop Bus Propagation Delays
Name tP DX Device SPECTRA155 Description DCK High to Dx Valid Min 3 Max 20
The input constraints involved in Figure 16 are shown in the following table: Table 4 Telecom Drop Bus Timing Constraints
Name tS DFP tH DFP tS TEL tH TEL Device SPECTRA155 SPECTRA155 TEMUX-84 TEMUX-84 Description DFP Set-up Time DFP Hold Time Telecom Bus Set-up Time Telecom Bus Hold Time Min 5 1 5 1 Actual 25.72 25.72 31.44 3 Margin 20.72 24.72 26.44 2
5.1.2 SPECTRA-155 - TEMUX-84 Telecom ADD Bus The Telecom ADD Bus is the egress interface between SPECTRA data and control inputs and TEMUX data and control outputs. See Figure 17 below for a diagram of the Telecom ADD bus timing.
0ns 50ns 100ns 15
RCK, LREFCLK tS TEL tH TEL Valid LAC1 in tP TEL AC1J1V1 tP TEL tH Ax Telecom ADD Bus tS AC1 Valid In/Out tS Ax tH Ax tP TEL tH AC1 tP TEL Valid In/Out tS Ax tP TEL tP TEL Valid In/Out tS Ax
LAC1
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Figure 17 Telecom ADD Bus Timing Diagram In reference to Figure 17, the sequence of events for one Telecom ADD bus clock cycle is as follows: 1. The TEMUX-84 updates LADATA[7:0], LADP, and LAPL on the falling edge of LREFCLK after a propagation delay, tP TEL. 2. On the next rising edge, SPECTRA samples AD[7:0], ADP, and APL on the rising edge of ACK. These SPECTRA inputs require a set-up time of tS Ax and a hold time of tH Ax relative to the rising edge of ACK. 3. On the same rising edge of LREFCLK, the TEMUX-84 samples LAC1. LAC1 requires a set-up time of tS TEL and a hold time of tH TEL. The output propagation delays involved in Figure 17 are shown in the following table: Table 5 Telecom Add Bus Propagation Delays
Name tP TELOE tZ TEL tP TEL Device TEMUX84 TEMUX84 TEMUX84 Description LREFCLK to Tristateable Outputs going Valid from Tristate LREFCLK to Tristateable Outputs going Tristate LREFCLK to Output Valid Min 0 3 3 Max 13 20 20
The input constraints involved in Figure 17 are shown in the following table: Table 6 Telecom Add Bus Timing Constraints
Name tS TEL tH TEL tS Ax tH Ax tS AC1 tH AC1 Device SPECTRA155 SPECTRA155 SPECTRA155 SPECTRA155 TEMUX-84 TEMUX-84 Description Telecom Bus Set-up Time Telecom Bus Hold Time Ax Set-up Time Ax Hold Time AC1J1V1 Set-up Time AC1J1V1 Hold Time Min 5 1 5 1 5 1 Actual 25.72 25.72 31.44 3 31.44 3 Margin 20.72 24.72 26.44 2 26.44 2
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5.1.3 TEMUX-84 - S/UNI-IMA-84 SBI ADD Bus Interface The SBI ADD Bus is the egress interface between S/UNI-IMA-84 data and control outputs and TEMUX-84 data and control inputs. On the ADD bus, SREFCLK provides timing to the TEMUX-84 and REFCLK provides timing to the S/UNI-IMA-84. These clocks need to be synchronized for correct operation of the bus. The C1FP frame pulse indicates SBI bus multiframe alignment, which occurs every 500 s. Therefore, this signal is pulsed every 9720 SREFCLKs. In this reference design, C1FP is generated from the SDC1FP pin of the TEMUX-84. In reference to Figure 18, the S/UNI-IMA-84 outputs are ADATA[7:0], ADP, APL, AC1FP, and AV5. The corresponding TEMUX-84 inputs are SADATA[7:0], SADP, SAPL, SAC1FP, and SAV5. Please see the Pin Description and Functional Timing sections of the device datasheets for the functional description of these signals.
0ns
50n s
100ns
150ns
SREFCLK, REFLCK tP C1FPO UT C1FP Valid tP C1FP OUT tP C1FPO
AC1FP
tZ S AJUST _REQ tH AJUST_REQ tS AJUST _REQ tP S AJUST _REQ SADJUST_REQ tP SBIADD tS SBIADD tP S BIADD SBI ADD Bus tH SBIADD tP SBIA
Figure 18 SBI ADD Bus Timing Analysis In reference to Figure 18, the sequence of events for one SBI ADD bus clock cycle is as follows: 1. S/UNI-IMA-84 updates ADATA[7:0], ADP, APL, and AV5 on the rising edge of REFCLK after a propagation delay, tP SBIADD.
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2. On the same rising edge, TEMUX-84 updates C1FPOUT after a propagation delay, tP SDC1FP. 3. The AJUST_REQ signal is asserted by the TEMUX-84 to control the data rate of the S/UNI-IMA-84. 4. On the next rising edge of SREFCLK, TEMUX-84 samples SADATA[7:0], SADP, SAPL, and SAV5. These TEMUX-84 inputs require a set-up time of tS SBIADD and a hold time of tH SBIADD relative to the rising edge of SREFCLK. 5. On the same edge, the S/UNI-IMA-84 samples the SAJUST_REQ signal. The SAJUST_REQ signal requires a setup time of tSAJUST and a hold time of tHSAJUST The output propagation delays involved in Figure 18 are shown in the following table: Table 7 SBI Add Bus Propagation Delays
Name tP SBIADD tP SAJUST_REQ tZ SAJUST_REQ Device S/UNI-IMA-84 TEMUX-84 TEMUX-84 Description REFCLK to SBI ADD Bus Outputs Valid SREFCLK to SAJUST_REQ Valid SREFCLK to SAJUST_REQ Tri-state Min 0 2 2 Max 20 15 15
The input constraints involved in Figure 18 are shown in the following table: Table 8 SBI Add Bus Timing Constraints
Name tS AJUST tH AJUST tS SBIADD tH SBIADD Device S/UNI-IMA-84 S/UNI-IMA-84 TEMUX-84 TEMUX-84 Description SAJUST_REQ Set-up Time to SREFCLK SAJUST_REQ Hold Time to SREFCLK SBI ADD Bus Inputs Set-up Time to SREFCLK SBI ADD Bus Inputs Hold Time from SREFCLK Min 4 0 4 0 Actual 36.44 2 31.44 0 Margin 32.44 2 27.44 0
5.1.4 TEMUX-84 - S/UNI-IMA-84 SBI DROP Bus Interface The SBI DROP Bus is the ingress interface between TEMUX-84 data and control outputs and S/UNI-IMA-84 data and control inputs. On the DROP bus, SREFCLK provides timing to the TEMUX-84 and REFCLK provides timing to the
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S/UNI-IMA-84. These clocks need to be synchronized for correct operation of the bus. The C1FP frame pulse indicates SBI bus multiframe alignment, which occurs every 500 s. Therefore, this signal is pulsed every 9720 SREFCLKs. In this reference design, C1FP is generated from the SDC1FP pin of the TEMUX-84. In reference to Figure 19, theTEMUX-84 outputs are SDDATA[7:0], SDDP, SDPL, and SDV5. The corresponding S/UNI-IMA-84 inputs are DDATA[7:0], DDP, DPL, and DV5. Please see the Pin Description and Functional Timing sections of the device datasheets for the functional description of these signals.
0ns 50n s 100ns 150ns
SREFCLK, REFCLK tP C1FPO UT C1FP Valid tS SBIDROP tP S BIDROP SBI DROP Bus tP C1FP OUT tP C1FPO
DC1FP
tP SBIDROP tH SB IDROP tP SBIDRO
Figure 19 SBI DROP Bus Timing Analysis In reference to Figure 19, the sequence of events for one SBI DROP bus clock cycle is as follows: 1. On the rising edge of REFCLK, TEMUX-84 updates SDDATA[7:0], SDDP, SDPL, and SDV5 after a propagation delay, tP SBIDROP. 2. On the same edge, TEMUX-84 updates C1FP after a propagation delay, tP SDC1FP. 3. On the next rising edge of SREFCLK, S/UNI-IMA-84 samples DDATA[7:0], DDP, DPL, and DV5. These S/UNI-IMA-84 inputs require a set-up time of tS SBIDROP and a hold time of tH SBIDROP relative to the rising edge of SREFCLK. The output propagation delays involved in Figure 19 are shown in the following table: Table 9 SBI DROP Bus Propagation Delays
Name Device Description Min Max
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Name tP SBIDROP tP SDC1FP
Device TEMUX-84 TEMUX-84
Description REFCLK to SBI DROP Bus Outputs Valid SREFCLK to C1FP Valid
Min 0 2
Max 20 15
The input constraints involved in Figure 19 are shown in the following table:
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Table 10 SBI DROP Bus Timing Constraints
Name tS SBIDROP tH SBIDROP Device S/UNIIMA-84 S/UNIIMA-84 Description SBI DROP Bus Inputs Set-up Time to SREFCLK SBI DROP Bus Inputs Hold Time from SREFCLK Min 4 0 Actual 31.44 0 Margin 27.44 0
5.1.5 S/UNI-IMA-84 - S/UNI-DUPLEX UTOPIA Level 2 TRANSMIT Bus Interface The UTOPIA Level 2 is used as the standard for communication between the PHY to ATM layer device in this development kit. The PHY device being the S/UNI-IMA-84 and the ATM layer device being the S/UNI-DUPLEX. In the egress direction the S/UNI-DUPLEX will present the ATM cells, which will be mapped into multiple links by the S/UNI-IMA-84. Conversely, in the ingress direction the S/UNI-IMA-84 will extract the ATM cells from their respective links and present the ATM cells to the S/UNI-DUPLEX to be processed. This bus interface is configured to be a byte-wide interface with synchronous timing provided by an external 19.44MHz oscillator to each device's respective reference bus clock pins. The UTOPIA L2 Transmit Bus is the egress interface between S/UNI-IMA-84 data and control inputs and S/UNI-DUPLEX data and control outputs. As a bus master, the S/UNI-DUPLEX will continuously poll the Transmit Cell Available (TCA) status line of the S/UNI-IMA-84 for which it has a downstream cell buffered. When the S/UNI-IMA-84 has room (ie. TCA is asserted), the S/UNIDUPLEX sends the next buffered cell to the PHY over the UTOPIA L2 bus.
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0ns 1 Clock tP Duplex tH IMA RxAddr tP Duplex tH IMA RxEnb tZ IMA tH Duplex RxClav tZ Duplex tH IMA TxData[7:0], TxPrty, TxSOC, TxClav
25ns
50ns 2
75ns
tS IMA Valid Data tS IMS Valid Data
tH IMA tP Duplex
tS IMA
tH IMA tP Duplex
tS IMS
tZB tP IMA Valid Dat tZB Duplex tP Duplex Valid Dat tS IMA tS Duplex
Figure 20 UTOPIA L2 Bus Transmit Timing Diagram
In reference to Figure 20, the sequence of events for one UTOPIA Level 2 bus cycle is as follows: 1. On the rising edge of RxClk, signals RxAddr and RxEnb are updated by the S/UNI-DUPLEX after the propagation delay tP Duplex. 2. On the next rising edge of RxClk, the S/UNI-IMA-84 reads the data from the signals RxAddr and RxEnb. The S/UNI-IMA-84 requires that the data be valid during the setup time tS IMA and the hold time tH IMA. In addition, the S/UNI-IMA-84 can update RxClav after a propagation delay tP IMA. 3. Also on the same edge, the S/UNI-DUPLEX may update RxData[7:0], RxPrty, and RxSOC after a propagation delay tP Duplex. 4. On the next rising edge of RxClk, the S/UNI-IMA-84 reads the data from the signals RxData[7:0], RxPrty, RxSOC, and RxClav. The S/UNI-IMA-84 requires that the data be valid during the setup time tS IMA and the hold time tH IMA. In addition, the S/UNI-IMA-84 can update RxClav after a propagation delay tP IMA. The output propagation delays involved in Figure 20 are shown in the following table:
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Table 11 UTOPIA L2 Transmit Bus Propagation Delays
Name tP Duplex tZ Duplex tP Ima tZ Ima tZB Device S/UNI-Duplex S/UNI-IMA-84 S/UNI-IMA-84 S/UNI-IMA-84 S/UNI-IMA-84 Description Clock high to data valid Clock high to output high impedence Clock high to data valid Clock high to output high impedence Clock high to output driven Min 2 2 Max 12 12 12 12
0
The input constraints involved in Figure 20 are shown in the following table: Table 12 UTOPIA L2 Transmit Bus Timing Constraints
Name tS IMA tH IMA tS Duplex tH Duplex Device S/UNI-IMA-84 S/UNI-IMA-84 S/UNI-Duplex S/UNI-Duplex Description IMA Setup Time IMA Hold Time DUPLEX Setup Time DUPLEX Hold Time Min 4 0 3 1 Actual 18.3 2 16.3 12 Margin 14.3 2 13.3 11
5.1.6 S/UNI-IMA-84 - S/UNI-DUPLEX UTOPIA Level 2 RECEIVE Bus Interface The UTOPIA L2 Receive Bus is the ingress interface between the S/UNI-IMA-84 data and control outputs and the S/UNI-DUPLEX data and control inputs. As a bus master, the S/UNI-DUPLEX will continuously poll the Receive Cell Available (RCA) status line of the S/UNI-IMA-84, reading the cells from the S/UNI-IMA-84 as they become available. Once a cell is brought into the S/UNI-DUPLEX, the cell is tagged (via a prepend byte) with the appropriate PHY ID (0:31), and sent out simultaneously to the LVDS links.
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0ns 1 Clock tP IMA RxData[7:0], RxPrty, RxSOC, RxClav tP Duplex tH IMA RxAddr tP Duplex tH IMA RxEnb tZ tH Duplex RxClav
25ns
50ns 2
75ns
tS Duplex
tP IMA tH Duplex
tS Duplex
tS IMA Valid Data tS IMS Valid Data
tH IMA tP Duplex
tS IMA
tH IMA tP Duplex
tS IMS
tZB tP IMA Valid Da tS Duplex
Figure 21 UTOPIA L2 Bus Receive Timing Diagram In reference to Figure 21, the sequence of events for one UTOPIA Level 2 bus cycle is as follows: 1. On the rising edge of RxClk, signals RxAddr and RxEnb are updated by the S/UNI-DUPLEX after the propagation delay tP Duplex. 2. On the next rising edge of RxClk, the S/UNI-IMA-84 reads the data from the signals RxAddr and RxEnb. The S/UNI-IMA-84 requires that the data be valid during the setup time tS IMA and the hold time tH IMA. 3. Also on the same edge, the S/UNI-IMA-84 may update RxData[7:0], RxPrty, RxSOC, and RxClav after a propagation delay tP IMA. 4. On the next rising edge of RxClk, the S/UNI-DUPLEX reads the data from the signals RxData[7:0], RxPrty, RxSOC, and RxClav. The output propagation delays involved in Figure 21 are shown in the following table:
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Table 13 UTOPIA L2 Receive Bus Propagation Delays
Name tP Duplex tP Ima tZ tZB Device S/UNI-Duplex S/UNI-IMA-84 S/UNI-IMA-84 S/UNI-IMA-84 Description Clock high to data valid Clock high to data valid Clock high to output high impedance Clock high to output driven Min 2 Max 12 12 12
0
The input constraints involved in Figure 21 are shown in the following table: Table 14 UTOPIA L2 Transmit Bus Timing Constraints
Name tS IMA tH IMA ts Duplex tH IMA Device S/UNI-IMA-84 S/UNI-IMA-84 S/UNI-Duplex S/UNI-IMA-84 Description IMA Setup Time IMA Hold Time DUPLEX Setup Time DUPLEX Hold Time Min 4 0 3 1 Actual 18.3 2 16.3 12 Margin 14.3 2 13.3 11
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5.1.7 PCI 9030 Timing Diagrams Timing specifications for the PCI 9030 that are specific to the microprocessor interface for the S/UNI-IMA-84/TEMUX-84 Development Kit is reproduced here. Table 15 PCI 9030 AC Timing (Local Inputs) Electrical Characteristics
Symbol LAD[0:31] LD[0:31] READY# Signal Name Address/Data Bus Data Bus Local Ready Input tSETUP 5.0 5.0 7.0 tHOLD 1.0 1.0 1.0 Units Ns Ns Ns
Table 16 PCI 9030 AC Timing (Local Outputs) Electrical Characteristics
Symbol ADS# CS[0:3] LA[2:27] LD[0:31] RD# WR# Signal Name Address Strobe Chip Select Address Bus Data Bus Read Strobe Write Strobe tLOUT 10.0 10.0 10.0 10.0 10.0 10.0 Units Ns Ns Ns Ns Ns Ns
Maximum output propagation delays are measured with a 50pF load on the outputs. The following sections describe the timing analysis performed for both read and write accesses to each PMC-Sierra device. Note that all timing margin requirements are met in the timing diagrams for each microprocessor read and write to PMC-Sierra devices. 5.1.7.1 TEMUX-84 READ Operation The host processor can access the registers on the TEMUX-84 device via the PCI 9030 Target Interface Device. The read access of the TEMUX-84 is shown below.
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0ns 1 Local Clk
50ns 2 3
100 ns 4
150ns 5
200ns 6 7
tPLOUT ADDR tP LOUT TEMUX_CS tP LOUT tS AR RD Valid Ad dress
tH AR tPLOUT
tP LOUT
tP LOUT
tZ RD tPRD DATA tS LIN tH LIN Valid Da ta
Figure 22 TEMUX-84 read cycle timing In reference to Figure 22, the sequence of events for the PCI 9030 to read data from any TEMUX-84 is as follows: 1. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI 9030 asserts the RD signal after a propagation delay of tP LOUT. The cycle in which the RD signal is asserted is set by the Read Strobe Delay bits in the LAS1BRD register of the PCI 9030. For this interface, the value is 1. 3. After the propagation delay tP RD, the TEMUX-84 puts valid data on the data bus. At the start of cycle 5, The PCI 9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tS LIN and a hold time of tH LIN. Note that the PCI 9030 waits 1 cycle for the data to be placed on the data bus, this delay is set by the NRAD bits in LAS1BRD. 4. Also at the start of cycle 5, the PCI 9030 de-asserts the RD, TEMUX_CS, and address lines after the propagation delay, tP LOUT. The de-assertion of the RD signal causes the TEMUX-84 data bus to tristate after a propagation delay tZ RD. The output propagation delays involved in Figure 22 are shown in the following table:
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Table 17 PCI 9030 to TEMUX-84 Read Propagation Delays
Name tP LOUT tP RD tZ RD Device PCI 9030 TEMUX-84 TEMUX-84 Description Local Clock edge to Local output delay RD to valid data delay RD negated to data tristate delay Min Max 10 30 20
The input constraints involved in Figure 22 are shown in the following table: Table 18 PCI 9030 to TEMUX-84 Read Timing Constraints
Name tS AR tH AR tS LIN tH LIN Device TEMUX-84 TEMUX-84 PCI 9030 PCI 9030 Description Address to valid read setup Address to valid read hold Input setup time Input hold time Min 10 5 5 1 Actual 40 10 40 30 Margin 30 5 35 29
5.1.7.2 TEMUX-84 WRITE Operation The write access of the TEMUX-84 is shown below.
0ns 1 Local Clk
50ns 2 3
100 ns 4
150ns 5
200ns 6
tP LOUT ADDR tP LOUT TEMUX_CS tP LOUT tS AW WR tS DW tP LOUT LDATA V alid Da ta tH DW tV WR tP LOUT tH AW Address Valid
tP LOUT
tP LOUT
tP LOUT
Figure 23 TEMUX-84 write cycle timing In reference to Figure 23, the sequence of events for the PCI 9030 to write data to the TEMUX-84 is as follows:
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1. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI 9030 puts valid data on the data bus and asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS1BRD register of the PCI 9030. For this interface, the value is 1. This delay is required to satisfy tS AW, the address to write setup time. 3. The TEMUX-84 inputs require the data to be present for a setup time of tS DW. To satisfy these requirements, the PCI 9030 waits 1 cycle with valid data on the data bus. The NWDD bits in LAS1BRD set the wait delay. This wait delay also satisfies tV WR, the Valid Write Pulse width. 4. On the rising edge of clock cycle 5, the PCI 9030 deasserts the WR signal after a propagation delay of tP LOUT. This causes the TEMUX-84 to latch the data from the bus. The data must remain present on the bus for an additional tH DW. This is accomplished by setting the Write Cycle Hold bits in LAS1BRD to 1. The write cycle hold causes DATA, TEMUX_CS, and ADDR to stay active until the rising edge of cycle 6, when they deassert after tP LOUT. The output propagation delays involved in Figure 23 are shown in the following table: Table 19 PCI 9030 to TEMUX-84 Write Propagation Delays
Name tP LOUT Device PCI 9030 Description Local Clock edge to Local output delay Min Max 10
The input constraints involved in Figure 23 are shown in the following table: Table 20 PCI 9030 to TEMUX-84 Write Timing Constraints
Name tS AW tV WR tH AW tS DW tH DW Device TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 TEMUX-84 Description Address to valid write set-up Valid write pulse width Address to valid write hold Data to valid write set-up Data to valid write hold Min 10 40 5 20 5 Actual 40 80 40 80 40 Margin 30 40 35 60 35
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5.1.7.3 S/UNI-DUPLEX READ Operation The host processor can access the registers on the S/UNI-DUPLEX device via the PCI 9030 Target Interface Device. The read access of the S/UNI-DUPLEX is shown below.
0ns 1 Local Clk
50n s 2 3
100ns 4
150ns 5
200ns 6
250ns 7
tPLOUT ADDR tP LOUT DUPLEX_CS tP LO UT tS AR RD Valid Address
tH AR tPLOUT
tP LOUT
tP LOUT
tZ RD tPRD DATA tS LIN tH LIN Valid Data
Figure 24 S/UNI-DUPLEX READ Timing Diagram In reference to Figure 24, the sequence of events for the PCI 9030 to read data from any S/UNI-DUPLEX is as follows: 5. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 6. On the rising edge of clock cycle 3, the PCI 9030 asserts the RD signal after a propagation delay of tP LOUT. The cycle in which the RD signal is asserted is set by the Read Strobe Delay bits in the LAS1BRD register of the PCI 9030. For this interface, the value is 1. 7. After the propagation delay tP RD, the S/UNI-DUPLEX puts valid data on the data bus. At the start of cycle 6, The PCI 9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tS LIN and a hold time of
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tH LIN. Note that the PCI 9030 waits 2 cycles for the data to be placed on the data bus, this delay is set by the NRAD bits in LAS1BRD. 8. Also at the start of cycle 6, the PCI 9030 de-asserts the RD, DUPLEX _CS, and address lines after the propagation delay, tP LOUT. The de-assertion of the RD signal causes the S/UNI-DUPLEX data bus to tristate after a propagation delay tZ RD. The output propagation delays involved in Figure 24 are shown in the following table: Table 21 PCI 9030 to S/UNI-DUPLEX Read Propagation Delays
Name tP LOUT tP RD tZ RD Device PCI 9030 S/UNIDUPLEX S/UNIDUPLEX Description Local Clock edge to Local output delay RD to valid data delay RD negated to data tristate delay Min Max 10 70 20
The input constraints involved in Figure 24 are shown in the following table: Table 22 PCI 9030 to S/UNI-DUPLEX Read Timing Constraints
Name tS AR tH AR tS LIN tH LIN Device S/UNIDUPLEX S/UNIDUPLEX PCI 9030 PCI 9030 Description Address to valid read setup Address to valid read hold Input setup time Input hold time Min 10 5 5 1 Actual 40 10 40 30 Margin 30 5 35 29
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5.1.7.4 S/UNI-DUPLEX WRITE Operation The write access of the S/UNI-DUPLEX is shown below.
0ns 1 Local Clk
50ns 2 3
100 ns 4
150 ns 5
200ns 6
tP LOUT ADDR tP LOUT DUPLEX_CS tP LOUT tS AW WR tS DW tP LOUT DATA Valid Data tH DW tV WR tP LOUT tH AW Address Valid
tP LOUT
tP LOUT
tP LOUT
Figure 25 S/UNI-DUPLEX WRITE Timing Diagram In reference to Figure 25, the sequence of events for the PCI 9030 to write data to the S/UNI-DUPLEX is as follows: 5. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 6. On the rising edge of clock cycle 3, the PCI 9030 puts valid data on the data bus and asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS1BRD register of the PCI 9030. For this interface, the value is 1. This delay is required to satisfy tS AW, the address to write setup time. 7. The S/UNI-DUPLEX inputs require the data to be present for a setup time of tS DW. To satisfy these requirements, the PCI 9030 waits 2 cycles with valid data on the data bus. The NWDD bits in LAS1BRD set the wait delay. This wait delay also satisfies tV WR, the Valid Write Pulse width.
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8. On the rising edge of clock cycle 5, the PCI 9030 deasserts the WR signal after a propagation delay of tP LOUT. This causes the S/UNI-DUPLEX to latch the data from the bus. The data must remain present on the bus for an additional tH DW. This is accomplished by setting the Write Cycle Hold bits in LAS1BRD to 1. The write cycle hold causes DATA, DUPLEX _CS, and ADDR to stay active until the rising edge of cycle 6, when they deassert after tP LOUT. The output propagation delays involved in Figure 23 are shown in the following table: Table 23 PCI 9030 to S/UNI-DUPLEX Write Propagation Delays
Name tP LOUT Device PCI 9030 Description Local Clock edge to Local output delay Min Max 10
The input constraints involved in Figure 23 are shown in the following table: Table 24 PCI 9030 to S/UNI-DUPLEX Write Timing Constraints
Name tS AW tV WR tH AW tS DW tH DW Device S/UNIDUPLEX S/UNIDUPLEX S/UNIDUPLEX S/UNIDUPLEX S/UNIDUPLEX Description Address to valid write set-up Valid write pulse width Address to valid write hold Data to valid write set-up Data to valid write hold Min 10 40 5 20 5 Actual 40 80 40 80 40 Margin 30 40 35 60 35
5.1.7.5 S/UNI-IMA-84 READ/WRITE Operation PCI 9030 read/write access to the S/UNI-IMA-84 device is identical to that of read/write access to the S/UNI-DUPLEX device in terms of the timing requirements. The difference between these two operations for each device is the size of the address and data bus with which each device communicates with the PCI 9030. S/UNI-IMA-84 contains a 10-bit address bus and a 16-bit data bus, while the S/UNI-DUPLEX contains an 8-bit address and 8-bit data bus.
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5.1.7.6 SPECTRA-155 READ Operation PCI 9030 read access to the SPECTRA-155 device is similar to that of read access to the TEMUX-84. However, there are a few important differences. First, the data propagation delay is longer, requiring a maximum of 80 ns, as opposed to 40 ns for the TEMUX-84. Also, the address set up time requirement; TSAR is 25 ns, as opposed to 10 ns. To facilitate these differences, PCI 9030 chip select CS2 is used to generate chip selects for the SPECTRA-155. Using CS2 allows 2 wait states to be inserted for both read and write operations. A timing diagram for PCI 9030 read access to the SPECTRA-155 is presented in Figure 26. Note that all set-up and hold time requirements are met.
0ns 1 LCLK t LOUT ADDR[1:10] t LOUT SPECTRA_CS 2 3
100ns 4 5
200ns 6 7 8
tHAR t LOUT V alid Ad dress t LOUT
t LOUT tSAR WR tZRD tP RD DATA[7..0] tSLIN tHLIN Valid Data t LOUT
Figure 26 SPECTRA-155 read cycle timing In reference to Figure 26, the sequence of events for the PCI 9030 to read data from the SPECTRA-622 is as follows: 1. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tPLOUT. 2. On the rising edge of clock cycle 3, the PCI 9030 asserts the RD signal after a propagation delay of tPLOUT. The cycle in which the RD signal is asserted
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is set by the Read Strobe Delay bits in the LAS0BRD register of the PCI 9030. For this interface, the value is 1. 3. After the propagation delay tPRD, the SPECTRA-155 puts valid data on the data bus. At the start of cycle 6, The PCI 9030 reads the data from the data bus. The PCI 9030 inputs require a setup time of tSLIN and a hold time of tHLIN. Note that the PCI 9030 waits 5 cycles for the data to be placed on the data bus; the NRAD bits in LAS0BRD set this delay. 4. Also at the start of cycle 6, the PCI 9030 de-asserts the RD, CS, and address lines after the propagation delay, tPLOUT. The de-assertion of the RD signal causes the SPECTRA-155 data bus to tristate after a propagation delay tZRD. The output propagation delays involved in Figure 26 are shown in the following table: Table 25 PCI 9030 to SPECTRA-155 Read Propagation Delays
Name tLOUT tPRD TZRD Device PCI 9030 SPECTRA-155 SPECTRA-155 Description Local Clock edge to Local output delay RD to valid data delay RD negated to data tristate delay Min N/A N/A N/A Max 10 80 20
The input constraints involved in Figure 26 are shown in the following table: Table 26 PCI 9030 to SPECTRA-155 Read Timing Constraints
Name tSAR tHAR tSLIN tHLIN Device SPECTRA-155 SPECTRA-155 PCI 9030 PCI 9030 Description Address to valid read setup Address to valid read hold Input setup time Input hold time Min 25 5 5 1 Actual 40 10 30 30 Margin 15 5 25 29
5.1.7.7 SPECTRA-155 WRITE Operation The PCI 9030 write interface to the SPECTRA-155 device is similar in operation to write access to the TEMUX-84, with the exception that CS2B is used rather that CS3B (as noted in section 6.1.5.6). Figure 27 presents the SPECTRA-155 write cycle timing diagram.
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0ns 1 LCLK tP LOUT ADDR[10..1] tP LOUT SPECTRA_CS RD 2 3
100ns 4 5
200ns 6 7
tP LOUT A ddress Valid tP LOUT
tP LOUT tS AW WR tS DW tP LOUT DATA[7..0] Valid Data tV WR
tP LOUT tH AW
tP LOUT tH DW
Figure 27 SPECTRA-155 write cycle timing
In reference to Figure 27, the sequence of events for the PCI 9030 to write data to the SPECTRA-155 is as follows: 1. On the rising edge of clock cycle 2, the PCI 9030 outputs the required address and the appropriate chip select after a propagation delay of tP LOUT. 2. On the rising edge of clock cycle 3, the PCI 9030 puts valid data on the data bus and asserts the WR signal after a propagation delay of tP LOUT. The cycle in which the WR signal is asserted is set by the Write Strobe Delay bits in the LAS0BRD register of the PCI 9030. For this interface, the value is 1. This delay is required to satisfy tS AW, the address to write setup time. 3. The SPECTRA-155 inputs require the data to be present for a setup time of tS DW and a hold time of tH DW. To satisfy these requirements, the PCI 9030 waits 2 cycles with valid data on the data bus. The NWDD bits in LAS0BRD set the wait delay. This wait delay also satisfies tV WR, the Valid Write Pulse width. 4. On the rising edge of clock cycle 5, the PCI 9030 deasserts the WR signal after a propagation delay of tP LOUT. This causes the SPECTRA-155 to latch the data from the bus. The data must remain present on the bus for an additional tH DW. This is accomplished by setting the Write Cycle Hold bits
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in LAS0BRD to 1. The write cycle hold causes DATA, SPECTRA_CS, and ADDR to stay active until the rising edge of cycle 6, when they deassert after tP LOUT. The output propagation delay involved in Figure 27 are shown in the following table: Table 27
Name tP LOUT
PCI 9030 to SPECTRA-622 Write Propagation Delays
Device PCI 9030 Description Local Clock edge to Local output delay Min Max 10
The input constraints involved in Figure 27 are shown in the following table: Table 28
Name tS AW tV WR tH AW tS DW tH DW
PCI 9030 to SPECTRA-622 Write Timing Constraints
Device SPECTRA-155 SPECTRA-155 SPECTRA-155 SPECTRA-155 SPECTRA-155 Description Address to valid write set-up Valid write pulse width Address to valid write hold Data to valid write set-up Data to valid write hold Min 25 40 5 20 5 Actual 40 80 40 80 40 Margin 15 40 35 60 35
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5.2
SIGNAL INTEGRITY SIMULATIONS
5.2.1 Pre-Layout The following sections contain pre-layout signal integrity simulations for the Telecom, SBI, UTOPIA L2 and PCI 9030 bus interfaces of the S/UNI-IMA84/TEMUX-84 Development Kit. The simulations were performed using the SPECTRA-155, TEMUX-84, S/UNI-IMA-84 and S/UNI-DUPLEX IBIS models. 5.2.2 Telecom Bus
U(A0) PM5342_SPECTRA SS[0] CELL:A0 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B0 65.8 ohms 439.225 ps 2.500 in Stripline CELL:C0 56.0 ohms RS(C0)
U(D0) PM8316_TEMUX_84 ladata_0 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D0
ADD BUS
U(A1) PM5342_SPECTRA SS[2] CELL:A1 56.0 ohms RS(A1) 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B1 65.8 ohms 439.225 ps 2.500 in Stripline CELL:C1 U(D1) PM8316_TEMUX_84 lddata_0 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D1
DROP BUS
Figure 28 Telecom Bus Simulation Schematic
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7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
Figure 29 Telecom DROP Bus Simulation Results
7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
Figure 30 Telecom ADD Bus Simulation Results Simulation results for 0 and 56 termination values for the ADD and DROP buses are presented in the above figures. It is clear that with 0 terminations (right) more overshoot, undershoot, and ringing occurs than with the 56 terminations.
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5.2.3 SBI Bus
U(A0) PM8316_TEMUX_84 sadata_0_mved_5 CELL:A0 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B0 73.7 ohms 527.070 ps 3.000 in Stripline CELL:C0 56.0 ohms RS(C0)
U(D0) PM7341_IMA84 adata[0] 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D0
ADD Bus
U(A1) PM8316_TEMUX_84 sddata_0_mvid_4 CELL:A1 56.0 ohms RS(A1) 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B1 73.7 ohms 527.070 ps 3.000 in Stripline CELL:C1 U(D1) PM7341_IMA84 ddata[0] 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D1
DROP Bus
Figure 31 SBI Bus Simulation Schematic
7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
Figure 32 SBI ADD Bus Simulation Results
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7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 10 nsec/div 100.000ns
Figure 33 SBI DROP Bus Simulation Results Simulation results for 0 and 56 termination values for the ADD and DROP buses are presented in the above figures. It is clear that with 0 terminations (right) more overshoot, undershoot, and ringing occurs than with the 56 terminations. 5.2.4 UTOPIA L2 Bus
U(A0) PM7341_IMA84 RDAT[0] CELL:A0 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B0 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C0 56.0 ohms RS(C0)
U(D0) PM7350_DUPLEX ODAT[0] 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D0
Transmit Bus
U(A1) PM7341_IMA84 TDAT[0] CELL:A1 56.0 ohms RS(A1) 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:B1 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C1 U(D1) PM7350_DUPLEX IDAT[0] 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D1
Receive Bus
Figure 34 UTOPIA L2 Bus Simulation Schematic
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7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 5 nsec/div 50.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 5 nsec/div 50.0ns
Figure 35 UTOPIA L2 RECEIVE Bus Simulation Results
7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0.0ns 5 nsec/div 50.0ns
1 V/div 0.0 volts -2.0 volts 0.0ns 5 nsec/div 50.0ns
Figure 36 UTOPIA L2 TRANSMIT Bus Simulation Results Simulation results for 0 and 56 termination values for the RECEIVE and TRANSMIT buses are presented in the above figures. It is clear that with 0 terminations (right) more overshoot, undershoot, and ringing occurs than with the 56 terminations.
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PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
5.2.5 PCI 9030 Interface
U(D0) PM7341_IMA84 d[1] CELL:B0 65.8 ohms 527.070 ps 3.000 in Stripline CELL:C0 22.0 ohms RS(C0) 82.9 ohms 29.225 ps 0.200 in Microstrip CELL:D0
U(D1) PM8316_TEMUX_84 d_1 CELL:B1 65.8 ohms 878.450 ps 5.000 in Stripline CELL:C1 22.0 ohms RS(C1) 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D1
PCI9030C_LBGA_3... CELL:B2 65.8 ohms 175.690 ps 1.000 in Stripline CELL:C2 33.0 ohms RS(C2) 79.0 ohms 28.787 ps 0.200 in Microstrip
U(D2) LD1 CELL:D2
PM7350_DUPLEX CELL:B3 65.8 ohms 702.760 ps 4.000 in Stripline CELL:C3 22.0 ohms RS(C3) 79.0 ohms 28.787 ps 0.200 in Microstrip
U(D3) D[1] CELL:D3
U(D4) PM5342_SPECTRA D[1] CELL:B4 65.8 ohms 1.054 ns 6.000 in Stripline CELL:C4 22.0 ohms RS(C4) 79.0 ohms 28.787 ps 0.200 in Microstrip CELL:D4
Figure 37 PCI 9030 Simulation Schematic
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58
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
7.0 volts
7.0 volts
1 V/div 0.0 volts -2.0 volts 0ns
1 V/div 0.0 volts -2.0 volts
5 nsec/div
50ns
0ns
5 nsec/div
50ns
Figure 38 PCI 9030 Simulation Results Simulation results for no termination (0 ) and series termination (22 and 33 ) for the PCI 9030 interface are presented in the above figures. It is clear that with no termination (right), more overshoot, undershoot, and ringing occurs than with the termination resistors.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
59
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
5.3
POWER ESTIMATE AND THERMAL ANALYSIS Table 29 Power Consumption by Supply Rail for Each Device Power (mW) 1.8V S/UNI-IMA-84 TEMUX-84 TOTAL 1.8V 929 1350 2579 Current (mA) 516 750 1266
3.3V S/UNI-IMA-84 S/UNI-DUPLEX TEMUX-84 PCI 9030 P149FCT3807 x2 Xilinx XC9536XL TOTAL 3.3V 5.0V SPECTRA-155 HFCT-5905E TOTAL 5.0V
396 1097 224 495 792 100 3104
120 333 68 150 240 33 944
725 770 1495
145 154 299
The total power requirements for the board are:
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60
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
TOTAL
7178mW
2509mA
These numbers are preliminary and may be revised in the future.
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61
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
6 6.1
DESIGN ISSUES Power Supply
6.1.1 Decoupling One 0.01uF and 0.1uF capacitor is required for every two digital power pins. The capacitors should be placed as close to the actual pin as possible. The analog power supply pins require a filtering network between the GND plane and the +3.3V plane. The network is a single RC network with a resistor between the 3.3V plane and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to Appendix A: Bill of Materials for component values. 6.1.2 Power-Up Sequence The power up sequence must be adhered to, otherwise device latchup can occur. The power supplies must turn on in the following sequence: 1. 5V Power 2. 3.3V Power 3. 1.8V Power The power down of the card must be performed in the reverse sequence. The delaying of the 1.8V digital power versus the 3.3V digital power is the critical factor since 1.8V is the core supply voltage for some of the devices and must come up after the 3.3V I/O supply voltage. The delaying of analog supplies to come up after its digital counterpart is easily accomplished by the analog supply filtering components. Since it takes time to charge the filter capacitors, the charging delays the analog supply rail a reasonable amount of time for the digital power to stabilize. If the simple solution of a filtering network cannot be implemented, then the analog power pins should be current limited to the maximum latch-up current of 100mA.
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62
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
6.2
SPECTRA-155 Design Considerations Analog power pins QAVD, RAVD and TAVD must be applied after VDD. A simple solution is to use a small filtering network between the VDD and AVD plane to delay the power to the AVD plane, which will delay power to each AVD pin. The following scheme is implemented on the S/UNI-IMA-84/TEMUX-84 Development Kit: * * Digital supply pins (VDD) are decoupled with 0.1F capacitors providing high frequency bypassing near the device pins. Analog supply pins (TAVD, RAVD, QAVD) are bypassed from the +5V power plane with five separate RC filters consisting of a series resistance and bypass capacitance. Groupings and values are as follows: * * * * * QAVD1, 2, 3: 4.7 series; 10F, 0.1F, 0.01F capacitor to ground RAVD1, 3, 4: 4.7 series; 10F, 0.1F, 0.01F capacitor to ground TAVD1, 3: 10 series; 10F, 0.1F, 0.01F capacitor to ground RAVD2: 4.7 series; 47F, 0.1F, 0.01F capacitor to ground TAVD2: 4.7 series; 47F, 0.1F, 0.01F capacitor to ground
6.3
TEMUX-84 Design Considerations The clock signals XCLK_T1 and XCLK_E1 must be carefully routed from the clock buffers to the TEMUX-84 parts. The lines should be properly terminated and should not run near any of the data busses if possible.
6.4
S/UNI-DUPLEX Design Considerations The S/UNI-DUPLEX should be placed so that there are no major components and the smallest distance possible between the S/UNI-DUPLEX and the LVDS connectors. The length of the traces in each of the LVDS line pairs should be kept the same to ensure correct impedance on the transmission line.
6.5
Telecom, SBI, UTOPIA L2 Bus Design Considerations Each signal on the bus requires adequate termination to prevent reflections. At each point where a bus line connects to a device, a series resistor should be
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63
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
placed on the line so that the source impedance of the line driver plus the impedance of the series resistor is matched to the characteristic impedance of the line. 6.6 PCI Bridge Design Considerations During power up, the PCI RST# signal resets the default values of the PCI 9030 internal registers. In return, the PCI 9030 outputs the local reset signal (LRESET#) and checks for the existence of the serial EEPROM. If a serial EEPROM is installed, and the first 16-bit word word is not FFFF, the PCI 9030 initializes the internal registers from the serial EEPROM. Otherwise, default values are used. The PCI 9030 configuration registers can only written by the optional serial EEPROM or the PCI host processor. During the serial EEPROM initialization, the PCI 9030 response to PCI target accesses is RETRYs.
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64
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
7 7.1
LAYOUT DESCRIPTION Component Placement The overall placement strategies of the components are: * * * * * Place the analog circuitry away from the digital circuitry. Keep analog transmit side components separate from the analog receive side components. For all high-speed data lines, load termination resistors are placed near the receiver inputs. For all high-speed data lines, source termination resistors are placed near the driver outputs. The Telecom bus, SBI bus should be routed so that the bus length is approximately the same to the TEMUX-84 from the SPECTRA-155 and the S/UNI-IMA-84. The PCI Bridge and the CPLD should be placed so that the I/O interface bus can be routed perpendicular to the Telecom/SBI buses. All pull up/down resistors are placed near the output pins. Oscillators should be placed in quiet digital sections as noise on their power supply will cause jitter on the output, and the oscillators themselves generate noise that may affect sensitive analog circuits. The PCI Bridge device is placed such that all the PCI interface traces are within the specified length limits of the PCI Rev. 2.1 Specification. All decoupling capacitors are placed near the power supply pins. The power supply should be placed in a low-component density area of the board so that sufficient copper on the component layer can be used for heatsinking of the supply regulators. Use a single plane for both analog and digital grounds.
* * *
* * *
*
The approximate placement of major components is shown in Figure 39 below. (The diagram is drawn to scale.)
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65
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
6U Euro Card Form Factor
50 100 150
CPCI
200
250
VOLTAGE REGULATORS
S/UNI-IMA-84
Oscillators
TEMUX-84
PLX PCI 9030
160 mm
Oscillators
LEDS
SDRAM
SPECTRA-155
CPLD
S/UNI DUPLEX
10 mm
OPTICS
LVDS
233.35 mm
Figure 39 Card Floorplan
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66
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
7.2 7.3
Layer Stacking and Impedance Control PCI Bus Signal Specification This layout follows the PCI Rev. 2.1 Specification layout restrictions. The PCI SIG specification has stringent and detailed rules on decoupling, power consumption, trace length limits, routing, trace impedance, as well as signal loading. Therefore, it is essential to check the latest PCI specification before proceeding with new designs and layouts. The S/UNI-IMA-84/TEMUX-84 Development Kit design board conforms to the following PCI Specification/Recommendations: * * * * * Component height on the component side does not exceed 0.570 inches, and on the solder side does not exceed 0.105 inches. PCI CLK signal trace is 2.5 inches +/- 0.1 inches and is connected to only one load. All 32-bit interface signals have the maximum trace length of 1.5 inches. Trace impedance for shared PCI signals are within 60 - 100 Ohm range, and trace velocity is between 150 and 190 ps/inch. 20 mil wide traces are used to connect the power and ground pins on PCI connector to their respective planes and the trace lengths are limited to 250 mil.
7.4
Routing * * * * All power and ground traces are as wide and as short as possible to minimize trace inductance. All high-speed traces are routed over continuous image planes (power or ground planes). All traces carrying transmit and receive line rate data should be routed on the same side and kept as short as possible. Both signals of a differential pair should be of equal length and routed close to each other.
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67
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
8 8.1
PHYSICAL AND MECHANICAL DESCRIPTIONS Form Factor The card is based on the CPCI 6U (233.35 mm by 160 mm) board size.
8.2
LEDs Several LEDs will be used on the front panel to indicate the status of the SONET/SDH links and the status of the card power supply. See below for a description of all status LEDs.
8.2.1 Card Status LEDs * * * * +5 V, super-red - indicates presence of +5 V +3.3 V, super-red - indicates presence of +3.3 V +1.8V super-red - indicates presence of +2.5 V RESET, super-red - indicates whether a reset condition exists on the board.
8.2.2 SPECTRA-155 LED's * * * * SALM (Section Alarm), red - Asserted when OOF, LOS, LOF, LAIS, or LRDI alarm conditions exist. LOF (Loss of Frame), red - Asserted when a Loss of Frame persists for more than 3 ms. LOS (Loss of Signal), red - Asserted when a violating period (20 2.5 s) of consecutive all zeros pattern is detected in the incoming stream. LAIS (Line Alarm Indication), red - Asserted when an AIS (Alarm Indication Signal) is detected in the incoming stream (111 pattern in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames). LRDI (Line Remote Defect Indication), red - Asserted when line RDI (Remote Defect Indication) is detected in the incoming stream (110 pattern in bits 6, 7 and 8 of the K2 byte for three or five consecutive frames).
*
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68
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
*
RALM <3..1> (Receive Alarm), red - Asserted when the following alarm conditions exist in the incoming stream: LOP (Loss of Pointer), PAIS (Path Alarm Indication), PRDI (Path RDI), PERDI (Path Enhanced RD), LOM (Loss of Multiframe), LOPCON (Loss of Pointer Concatenation), or PAISCON (Path AIS Concatenation).
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69
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
9 9.1
SOFTWARE INTERFACE System Processor Requirement The S/UNI-IMA-84/TEMUX-84 Development Kit must be accompanied with a CPU processor card on the same CPCI shelf.
9.2
S/UNI-IMA-84/TEMUX-84 Development Kit Operating System The S/UNI-IMA-84/TEMUX-84 Development Kit supports the VxWorks real time operating system (RTOS). The device drivers for the Development Kit's chipsets are pre-ported for VxWorks.
9.3
Device Drivers Upon request, PMC-Sierra Inc. provides drivers for each PMC-Sierra chip mounted on the Development Board.
9.4
S/UNI-IMA-84/TEMUX-84 Development Kit Memory Map Table 30 lists the memory map for the S/UNI-IMA-84/TEMUX-84 Development Kit. Table 30 S/UNI-IMA-84/TEMUX-84 Development Kit Memory Map
ADDRESS RANGE DEVICE CHIP SELECT
PCI 9030 CHIP SELECT CS0 CS1 CS2 CS3
0x00000 - 0x40000 0x40000 - 0x80000 0x80000 - 0xC0000 0xC0000 - 0x100000
SPECTRA-155 TEMUX-84 S/UNI-IMA-84 S/UNI-DUPLEX
SPECTRA_CS TEMUX_CS IMA_CS DUPLEX_CS
Within this development kit, there is a local bus on which one 16-bit device (S/UNI-IMA-84), and three 8-bit devices (SPECTRA-155, TEMUX-84, S/UNIDUPLEX) reside. Dealing with this constraint allowed for two possibilities. One would have been to use the 9030's ability to dynamically interface a 32-bit PCI bus to 8- and 16-bit local busses. While this option would have maximized memory efficiency on the CPU side, it also would have increased the design's complexity, both in hardware and in software. The option that was chosen for this reference design was to treat all devices as if they were 32 bit devices. All devices are assigned a 32-bit address space by the
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70
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
CPU. In the case of the 8-bit devices, 24 bits of every CPU lword are ignored. For the 16-bit device, 16 bits of the CPU lwords are ignored. The disadvantage of this design choice is that more CPU memory is required. However, because the S/UNI-IMA-84/TEMUX-84 Development kit does not require a large amount of memory space, this design choice is acceptable, considering the reduction in complexity it offers. Address translation works as follows: For a 16-bit local bus, the 9030 expects all addresses to be lword (32-bit) aligned, causing all addresses to end with `00'. Because of this, the 9030 does not even provide the two lowest address bits on the Local address bus. To accommodate this, every local address is mapped to an lword aligned boundary on the CPU side. i.e. register 0x0011 on the S/UNIDUPLEX is addressed as 0x0044on the CPU side.
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71
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
10
BOARD MODIFICATIONS
10.1 Signal Detect on HFCT 5905 The signal detect symbol on the HFCT 5905 part was pulled high externally to 3.7 V using a voltage divider and the +5V power source. This was necessary because the HFCT 5905 is a +3.3V part whereas the SPECTRA-155 is +5V part. It is recommended that a +5V optics module such as the HFCT 5205 be used instead of the HFCT 5905. The HFCT 5205 is implemented in the updated schematics. 10.2 UTOPIA L2 Bus On the S/UNI-IMA-84, the UTOPIA L2 Bus is connected to TADR_SCAN<0..4>, not TADR<7..10>. This change is reflected is the updated schematics. 10.3 SCANENB pin on S/UNI-IMA-84 The SCANENB pin on the S/UNI-IMA-84 should be pulled high externally via 4.7k pull-up resistor, not pulled low externally. This change is reflected in the updated schematics.
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72
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
11
GLOSSARY T1 A level 1 digital trunk operating at 1.544 Mbit/s that is popular in North America and Japan. It is made up of 193 bits, grouped as 1 framing bit followed by 24 DS-0 channels of 8 bits each. European First Order transmission format. This is the standardized (ITU-T G.704) base format of the European Pleisosynchronous Digital Hierarchy. It operates at 2.048Mbps. The E1 format consists of frames consisting of 32 octets, or timeslots (numbered 0 to 31). Timeslot 0 alternates between containing an FAS and containing the National Use bits (Sa[8:4]) and an A-bit for RAI. Timeslot 0 also contains an International Use Bit (Si) which can be used to support CRC Multiframe. Synchronous Payload Envelope Peripheral Component Interconnect - A bus standard that defines 32 bit transfers over a defined electrical interface. An adapter board for a PCI system which acts as a PCI Master and performs the additional functions of clock distribution and bus arbitration. An adapter board for a PCI system which does not initiate bus transactions. Also known as a slave. Compact Peripheral Component Interconnect. A bus standard based on the PCI standard that defines a more rugged mechanical form factor for industrial use. Serial EEPROM (Electrically Erasable Programmable Read Only Memory) - A type of non-volatile memory which is programmed and read using a serial interface.
E1
SPE PCI PCI Host
PCI Target CompactPCI
SEEP
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73
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
12
REFERENCES 1. PMC-Sierra Inc., PMC-1970133, "SPECTRA-155 SONET/SDH Payload Extractor/Aligner", August 1998, Issue 4. 2. PMC-Sierra Inc., PMC-1991437, "TEMUX-84 High Density 81 T1/63 E1 Framer with Integrated VT/TU Mappers and M13 Multiplexers", October 2000, Issue3. 3. PMC-Sierra Inc., PMC-2000223, "S/UNI-IMA-84 S/UNI Inverse Multiplexing for ATM, 84 Links", April 2000, Issue 2. 4. PMC Sierra Inc., PMC-1980581, "S/UNI-DUPLEX Dual Serial Link Phy Multiplexer Data Sheet", April 2000, Issue 5. 5. PCI Technology, PCI 9030-1 Data Book, Version 1.0, April 2000. 6. PCI Industrial Computer Manufacturers, CompactPCI PICMG, Revision 2.0, September 2, 1997.
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74
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
13
APPENDIX A: BILL OF MATERIALS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
75
Item 1 2
3
4 5 6
7 8
Description SURFACE MOUNT SWITCHING DIODE IC 3.3V 1:10 CMOS CLOCK DRIVER SOIC20W OCTAL BUFFER LINE DRIVER WITH 3 STATE OUTPUT, SOIC20W IC QUAD 2 IN AND GATE SOIC14 CAP 1.01UF 50V CERAMIC 0603 SMD MULTILAYER CERAMIC CHIP CAPACITOR X7R 0603 0.1UF 16V CAPR TANT 22UF EIA SIZE B CAP CERAMIC X7R 0603 50V 0.01UF
Part Number 1N4148W PI49FCT3807AS
Manufacturer VISHAY/LITEON PERICOM
Reference Designator D5 U6
Quantity 1 1
SN74HC540
TEXAS INSTRUMENTS
U2
1
MM74HC08M DIGIKEY PCC103BVCT-ND PANASONIC -ECJ-1VB1C104K
FAIRCHILD SEMI DIGI-KEY PANASONIC
U8 C321, C329, C344 C323, C326
1 3 2
PANASONIC ECU-V1H103KBV
PANASONIC PANASONIC
C1, C2 C12-C16, C27, C29, C30, C70, C77, C80, C82-C85, C87, C90, C91, C93, C95, C96, C98, C100-C108, C113, C114, C116C128, C131-C136, C138, C139, C145, C146, C149, C151, C153, C154, C156, C158-C160, C165, C166, C169, C171, C172, C177, C179C181, C183, C184, C188, C190-C192, C194, C200-C202 C53 C55 C3, C28, C35, C36, C39-C41, C49, C50, C52, C71-C76, C78, C79, C81, C86, C88, C89, C92, C94, C97, C99, C109-C112, C115, C129, C130, C137, C140-C144, C147, C148, C150, C152, C155, C157, C161-C164, C167, C168, C170, C173C176, C178, C182, C185-C187, C189, C193, C195-C199,
2 83
9 10 11
CAP CERAMIC X7R 0603 25V 0.022UF CAP CERAMIC X7R 0850 50V 0.047UF CAP CERAMIC X7R 0603 16V 0.1UF
ECJ-1VB1E223K 08055C473JATN ECJ-1VB1C104K
PANASONIC AVX PANASONIC
1 1 75
12 13 14 15 16 17 18 19
CAP CERAMIC X7R 0603 10V 0.22UF CAP CERAMIC X7R 1206 16V 0.33UF CAP CERAMIC NPO 0805 50V 1000PF CAP ELECTRO VA SMD 10V 20% 1000UF CAP TANCAPC 10V 20% 10UF CAP TANCAPA 6.3V 20% 10UF CAP TANCAPA 16V 20% 1UF CAP TANCAPD 10V 20% 33UF
ECJ-1VB1A224K ECJ-3VB1C334K ECU-V1H102JCX ECE-V1AA102P ECS-H1AC106R ECS-T0JY106R ECS-H1CY105R ECS-H1AD336R
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC
C203-C209 C62-C69 C54 C19 C43, C59 C4 C9-C11, C17, C18 C24, C44, C60 C20-C23, C25, C26, C31-C34, C37, C38, C42, C45-C47, C56C58 C48, C51 C7, C8 J10-J12
8 1 1 2 1 5 3 19
20 21 22
23
24
25
26
27 28
29 30
31
CAP TANCAPA 6.3V 20% 4.7UF CAP TANCAPD 6.3V 20% 47UF CONNECTOR 38 POS VERTICAL .025" TO .64" SMD MICTOR PART OF PCB COMPACT PCI ESD STRIP TRANSFORMER, DUAL, 10/100BASETX CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW CONN HEADER STRAIGHT 36POS MALE .1" SINGLE ROW CONN HEADER 8 PIN PITCH HEADER STRAIGHT SQUARE 3 ROW 1 POSITION/ROW TEMPERATURE 0C TO 70C 0.007 OHM, 20 V, HEXFET POWER MOSFET T-1 3/4 LED BLUE VERTICAL PCB MOUNT STATIC SENSITIVE
ECS-T0JY475R ECS-H0JD476R 2-767004-2
PANASONIC PANASONIC AMP
2 2 3
PART OF PCB
PART OF PCB
P1
1
H1026
PULSE ENGINEERING SULLINS ELECTRONICS
T1
1
PZC36SAAN
J13
1
PZC36SAAN
SULLINS ELECTRONICS
J7
1
PZC36SAAN 53047-0310
SULLINS MOLEX
J3, J4, J9 J5
3 1
HFCT-5205BD IRL3502S
HEWLETT PACKARD INTERNATIONA L RECTIFIER PANASONIC
U21 Q1, Q2
1 2
PANASONIC LNG91LCFB
D4
1
32
33
34 35 36
37 38
39
40 41
42
43
44
45
46
47
48 49 50
3A FAST ULTRA LOW DROPOUT LINEAR REGULATOR 1.8V TO263-5 4.6A LOW DROPOUT FIXED 3.3V REGULATOR HOT SWAP CONTROLLER GENERAL PURPOSE TRANSISTOR 2MM IEEE 1394-1995 SHIELD RIGHT ANGLE MOUNTING HOLE .150" DIA 3.3V, 100MHZ, 8MB SDRAM (1MBIT X 4BANKS X 16WIDE) 2048 BIT SERIAL EEPROM W/ DATA PROTECT AND SEQ READ DIP8 OSCILLATOR, 25MHZ, 3.3V, 50PPM OSCILLATOR 19.440MHZ 3.3V [TOL= 20PPM] [TEMP= 0-70C] [DUTY= 10%] OSCILLATOR 55.000MHZ 3.3V [TOL= 50PPM] [TEMP= 0-70C] [DUTY= 10%] OSCILLATOR 37.056MHZ 3.3V, 32PPM OSCILLATOR 49.152MHZ 3.3, 32PPM OSCILLATOR, 51.84MHZ, 3.3V, 50PPM RIGHT ANGLE PCB MOUNT SPST PUSH BUTTOM IC 3.3V PCI INTERFACE(180 PIN UBGA PACKAGE) POWER BLOCK RES 0603 1/16W 5% ZERO OHM RES 2512 1W 1% 0.01
LP3966ES-1.8
NATIONAL SEMI
U13
1
LT1585CT-3.3
LINEAR TECHNOLOGY LINEAR TECHNOLOGY MOTOROLA MOLEX
U16
1
LTC1422CS8 MMBT3904LT1 53460-0611
U15 Q3 J1, J2
1 1 2
MOUNTING HOLE MT48LC4M16A275 NM93CS56LEN
N/A MICRON
M1 U11
1 1
FAIRCHILD SEMI
U9
1
CB3LV-3C25.0000- T EH2645TS19.440M
CTS REEVES ECLIPTEK
Y2 Y1
1 1
EH2645TS55.000M
ECLIPTEK
Y6
1
EP2632TTS37.056M EP2632TTS49.152M EP2645TTS51.840M DIGIKEY -CKN4002-ND PCI9030-AA60BI
ECLIPTEK
Y5
1
ECLIPTEK
Y4
1
ECLIPTEK
Y3
1
DIGI-KEY
SW1
1
PLX TECHNOLOGY
U12
1
ERJ-3GSY0R00V WSL2512-R01-1
PANASONIC VISHAY
P2, P3 R200, R201 R107, R112
2 2 2
51 52 53 54 55 56 57 58 59 60 61 62 63 64
OHM RES 0603 1/16W 5% 1.0K OHM RES 0603 1/16W 5% 1.2K OHM RES 0603 1/16W 5% 10 OHM RES 0603 1/16W 5% 100 OHM RES 0603 1/16W 5% 100K OHM RES 0603 1/16W 5% 10K OHM RES 0805 1/10W 5% 10M OHM RES 0603 1/16W 5% 130 OHM RES 0603 1/16W 1% 2.43K OHM RES 0603 1/16W 5% 22 OHM RES 0603 1/16W 1% 237 OHM RES 0603 1/16W 5% 270 OHM RES 0603 1/16W 5% 3.0K OHM RES 0603 1/16W 5% 330 OHM
ERJ-3GSYJ102V ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3GSYJ101V ERJ-3GSYJ104V ERJ-3GSYJ103V ERJ-6GEYJ106V ERJ-3GSYJ131V ERJ-3EKF2431V ERJ-3GSYJ220V ERJ-3EKF2370V ERJ-3GSYJ271V ERJ-3GSYJ302V ERJ-3GSYJ331V
PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC
R7, R124 R199 R5, R19, R119, R125, R195 R8, R16 R198 R105 R31, R37, R83 R2, R3 R122 R78, R155, R158, R169, R170 R14, R15 R4 R6 R20, R32, R33, R35, R36, R38-R40, R51, R53, R56, R58, R61, R62, R66, R69-R73, R77, R91, R145-R147, R154, R156, R159, R162, R163, R174, R175, R178, R180R183, R185, R187R193, R202, R203 R17, R18, R29, R30, R34 R148 R1, R49, R50, R60, R63-R65, R68, R74, R81, R84, R88, R89, R93, R96, R98, R104, R106, R108-R111, R113-R118, R120, R126, R127, R149, R150, R152, R153, R157, R160, R161, R164, R166, R171R173, R197, R204 R196 R21-R24
2 1 5 2 1 1 3 2 1 5 2 1 1 47
65 66 67
RES 0603 1/16W 5% 4.7 OHM RES 0603 1/16W 1% 4.75K OHM RES 0603 1/16W 5% 4.7K OHM
ERJ-3GSYJ4R7V ERJ-3EKF4751V ERJ-3GSYJ472V
PANASONIC PANASONIC PANASONIC
5 1 45
68 69
RES 0603 1/16W 1% 47.5 OHM RES 0603 1/16W 1%
ERJ-3EKF47R5V ERJ-3EKF49R9V
PANASONIC PANASONIC
1 4
70
49.9 OHM RES 0603 1/16W 5% 56 OHM
ERJ-3GSYJ560V
PANASONIC
71 72
RES 0603 1/16W 1% 6.81K OHM RES 1.00M OHM 1/16W 1% 0603 SMD RES 1.0M OHM 1/10W 5% 0805 SMD RES 2.7 OHM 5% 0603
ERJ-3EKF6811V DIGI-KEY -PMHCTND DIGI-KEY -PACTND DIGI-KEY -PACTND DIGI-KEY -PGCTND DIGI-KEY -PGCTND DIGI-KEY -PGCTND DIGI-KEY -PGCTND DIGI-KEY -PGCTND DIGI-KEY -PGCTND PANASONIC -EXB-V8V100JV DIGI-KEY -Y4-ND PANASONIC -EXB-V8V330JV DIGI-KEY -Y4-ND
PANASONIC PANASONIC
R9, R10, R13, R25R28, R41-R48, R52, R54, R55, R57, R59, R67, R75, R76, R79, R80, R82, R85-R87, R90, R92, R94, R95, R97, R99-R103, R151, R165, R167, R168, R176, R179, R186, R194 R123 R130-R137
47
1 8
73
PANASONIC
R121
1
74
DIGI-KEY
R11, R12
2
75
RES 237 OHM 5% 0603 RES 330 OHM 5% 0603 RES 430 OHM 5% 0603 RES 49.9 OHM 5% 0603 RES 681 OHM 5% 0603 RES 750 OHM 1/16W 5% 0603 SMD RES ARRAY 10 OHM 5% 4 RES SMD RES ARRAY 22 OHM 5% 4 RES SMD
DIGI-KEY
R177
1
76
DIGI-KEY
R129, R138, R140
3
77
DIGI-KEY
R141, R143
2
78
DIGI-KEY
R128, R139
2
79
DIGI-KEY
R184
1
80
PANASONIC
R142, R144
2
81 82
PANASONIC PANASONIC
83 84
RES ARRAY 33 OHM 5% 4 RES SMD RES ARRAY 330 OHM 5% 4 RES SMD
PANASONIC PANASONIC
RN89-RN95, RN130RN13 5 RN5-RN10, RN12, RN14, RN25-RN30, RN35-RN37, RN45, RN49, RN63-RN67 RN71-RN77, RN83 RN21-RN24, RN31RN34, RN40, RN43, RN46, RN48, RN50, RN51, RN53, RN54, RN56-RN62, RN68RN70, RN78, RN79, RN96-RN103 , RN105,
13 24
8 50
85
RES ARRAY 4.7K OHM 5% 4 RES SMD
PANASONIC -EXB-V8V472JV
PANASONIC
86
RES ARRAY 470 OHM 5% 4 RES SMD RES ARRAY 56 OHM 5% 4 RES SMD
87
DIGI-KEY -Y4-ND PANASONIC -EXB-V8V560JV
PANASONIC
RN106, RN108-RN11 5, RN122-RN12 5 RN19, RN20, RN55, RN82, RN84-RN88, RN116-RN12 1, RN126-RN12 9 RN1, RN2
19
2
PANASONIC
88 89 90 91 92 93
94
95
96
97
SMB VERTICAL GOLD IC PMC SPECTRA-155 LED QUAD RED HORIZONTAL LED QUAD SUPER RED HORIZONTAL S/UNI-DUPLEX SCIPHY MODE IC S/UNI INVERSE MULTIPLEXING FOR ATM 84 LINKS IC HIGHSPEED CMOS QUAD 2 INPUT AND GATE SO14NB IC HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX IC IN SYSTEM PROGRAMMABLE CPLD PLCC44 CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD
903-499J-51P2 PM5342-BI SSF-LXH5147LID SSF-LXH5147SRD PM7350-PI PM7341
AMPHENOL PMC SIERRA LUMEX LUMEX PMC-SIERRA PMC SIERRA
RN3, RN4, RN11, RN13, RN15-RN18, RN38, RN39, RN41, RN42, RN44, RN47, RN52, RN80, RN81, RN104, RN107 J6, J8 U4 D1, D2 D3 U5 U7
19
2 1 2 1 1 1
TC74LVX08FN
TOSHIBA
U14
1
PM8316
PMC SIERRA
U10
1
XC9536XL7PC44C 352068-1
XILINX
U3
1
AMP
J15
1
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
14
APPENDIX B: SCHEMATICS
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
76
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
15
APPENDIX C: LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
77
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
16
APPENDIX D: VHDL CODE FOR CPLD
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
78
library IEEE; use IEEE.std_logic_1164.all;
entity myima is port ( osc: in STD_LOGIC; dfp: out STD_LOGIC; lac1: out STD_LOGIC; ctclk: inout STD_LOGIC; lrefclk: out STD_LOGIC; refclk: out STD_LOGIC; srefclk: out STD_LOGIC; trclk: out STD_LOGIC; ack: out STD_LOGIC ); end myima; architecture myima_arch of myima is begin -- FRAME PULSE GENERATION process (osc) variable COUNT_INT: integer range 0 to 10000; begin if osc='0' and osc'event then if COUNT_INT=9719 then LAC1 <='1'; DFP <='1'; COUNT_INT := 0; else COUNT_INT := COUNT_INT+1; LAC1 <='0'; DFP <='0'; end if; end if; end process; -- PROCESS sync8k_gen: Generates the 8kHz signal for the SBI bus. -- The process divide 19.44M by 2430 (2430/2-1=1214) process (osc) variable count2: integer range 0 to 5000; begin -count2 := 0; if osc'event and osc='1' then if count2=1214 then ctclk <= not ctclk; -- 8k clock count2 := 0; else count2 := count2 + 1; end if; end if; end process; -- Clock generation
lrefclk <= osc; srefclk <= osc; refclk <= osc; trclk <= osc; ack <= osc;
end myima_arch;
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
79
PRELIMINARY REFERENCE DESIGN PMC - 2002050 ISSUE 2
PM7341 S/UNI-IMA-84 PM8316 TEMUX-84
S/UNI-IMA-84/TEMUX-84 DEVELOPMENT KIT
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-2002050 (p2) Issue date: June 2001
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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